AI Software Solution Engineer focused on validation and workload enabling for Intel platforms. The role involves optimizing AI model efficiency, accuracy, and performance by working with frameworks, algorithms, and hardware. Key responsibilities include enabling AI models on Intel GPUs, debugging deep learning models, conducting benchmarking and validation, developing automation pipelines, and evaluating AI models against competitors. The role also involves customer engagement for enablement and performance improvements, and translating AI workload needs into architecture insights.

Engineer to work on Intel's AI frameworks software stack, focusing on design, development, and optimization of features for AI accelerators and GPUs. This includes ML kernel development, enhancing training and inference capabilities, and contributing to open-source AI frameworks like PyTorch, Tensorflow, and JAX.

Senior System Debug Engineer responsible for the design and development of integrated AI solutions for deep learning and machine learning systems, focusing on hardware, software, firmware, board, and silicon components. The role involves AI systems architecture, defining product specifications, and impacting the AI product roadmap. It requires developing new methods in various AI/ML domains, leading design and implementation of component-level choices for performance and cost, defining system integration approaches, and delivering end-to-end technical solutions. The role also includes debugging and ensuring the reliability of AI infrastructure, collaborating on next-generation requirements, and influencing AI roadmap with customer knowledge.

This role focuses on designing and developing features for Intel's AI frameworks software stack, specifically optimizing inference serving frameworks (like SGLang, vLLM) and ML frameworks (PyTorch, Tensorflow, JAX) for Intel's AI accelerators and GPUs. The engineer will enhance deep learning training and inference capabilities, identify optimization opportunities, and contribute to open-source communities.

Engineer to design and develop features for Intel's AI frameworks software stack, focusing on inference serving frameworks (SGLang, vLLM) and ML frameworks (PyTorch, Tensorflow, JAX). The role involves optimizing software for Intel's AI accelerators and GPUs, enhancing training and inference capabilities, and contributing to open-source communities.

This role focuses on building and maintaining scalable CI/CD systems and infrastructure for wireless connectivity solutions. A key aspect is designing and implementing AI-driven DevOps solutions to improve developer productivity, such as failure analysis, pipeline intelligence, workflow automation, or agent-based systems. The role involves extensive work with Jenkins, Kubernetes, Elastic Stack, Prometheus, Grafana, Ansible, Python, and Bash in Linux environments.

This role focuses on the design and implementation of AI System-on-Chip (SoC) hardware, including RTL design, microarchitecture, and integration. The engineer will collaborate with various teams to meet functional and performance goals for next-generation AI computing platforms.

AI Software Development Engineer at Intel, focused on building and debugging AI/ML systems, including prompt engineering, tool calling, and LLM-based workflows. The role involves designing, developing, and testing software for decision-making and analytics, with a focus on AI applications. Experience with C#, SQL, and AI concepts like RAG is required, with preferred experience in .NET, AI application design, and containerization.

This role focuses on debugging and resolving complex system-level issues for Intel's AI GPU product roadmap, involving hardware, software, firmware, and silicon components. The engineer will lead root-cause analysis, manage the bug lifecycle, and collaborate with cross-functional teams to ensure efficient resolution of platform issues and customer escalations. While familiarity with ML frameworks and AI/ML deployment debugging is a plus, the core responsibility is system-level engineering and debugging.

This role focuses on supporting customers in developing high-performance packet processing applications on Intel Architecture using DPDK and related software stacks. It involves acting as a technical consultant, developing demonstrations, benchmarks, and reference designs, and providing customer-facing documentation and support. The role also requires transitioning bare metal applications to cloud-native architectures and leveraging AI/ML tools for productivity enhancement, debugging, and code generation.

Senior Director to lead Enterprise Data & AI Enablement, defining strategic roadmaps for data and AI capabilities, building robust data foundations for advanced AI applications, and overseeing data strategy, architecture, ingestion, and governance. The role focuses on enabling AI/ML initiatives by providing necessary data infrastructure and tooling.

Lead a design verification engineering team for Intel's Silicon Chassis group, focusing on next-generation interconnect and coherent fabric IP. This player-coach role involves driving verification strategy, hands-on execution, and team building, with an emphasis on AI-assisted workflows and integrating ML-driven stimulus generation.

Solution Architect for Intel's Telco division in India, focusing on 5G network infrastructure and related technologies. The role involves bridging technical aspects with sales goals, influencing customers and partners to adopt Intel's products, and designing customized telecom solutions. Requires strong understanding of telecom, cloud, and AI concepts, with a focus on pre-sales and solution selling.

Performs functional verification of IP/Subsystem logic to ensure design meets specification requirements. Develops verification plans, test benches, and environments. Executes plans, runs simulation models, analyzes power/timing, and debugs issues in the presilicon environment. Collaborates with architects, RTL developers, and physical design teams. Maintains and improves verification infrastructure.

Senior Design Verification Engineer for Intel's Silicon Chassis team, responsible for owning verification of interconnect and chassis IP blocks. Requires expertise in verification planning, environment development, collaboration with cross-functional teams, and debugging. Experience with AI-assisted development tools is mentioned as part of the daily workflow.

Intel is seeking an IP Development Engineer with a Master's Degree in Electronics/VLSI/Computer Engineering. The role involves translating digital design concepts into RTL using System Verilog, developing microarchitectural specifications, coding RTL, running design tools, creating timing collateral, and supporting IP usage. Experience with functional bus protocols and JTAG is beneficial. Interest in automation using PERL/Python is a plus.

This role involves logic design and RTL development for Intel's Soft IP, contributing to microarchitectural specifications, coding, testing, and supporting IP deployment within SoCs. It requires a Master's degree in Electronics/VLSI/Computer Engineering and experience in Soft IP development.

This role focuses on developing, testing, and debugging software tools, flows, and methodologies for design automation within Intel's Central Engineering Group. The engineer will use Python, Unix, and TCL to streamline hardware design processes and optimize manufacturing, enabling breakthroughs in efficiency and performance for next-generation hardware products. While AI fundamentals are a preferred qualification, the core of the role is in EDA tools and automation, not direct AI/ML model development.

Analog Circuit Design Engineer with 1-2 years of experience in HIP development, circuit design, micro architectural specification, custom layout, and qualification of HIP to delivery standards. Requires experience with functional bus protocols and IEEE standards for test. Master's degree in Electrical/Computer Engineering preferred.

Performs physical design implementation of custom IP and SoC designs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, static timing analysis, power/clock distribution, reliability, and power/noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Optimizes design for power, frequency, and area, and participates in methodology development and flow automation.

IP Design Verification Engineer responsible for ensuring the reliability and functionality of IP designs by developing and executing verification plans, designing test benches, performing system simulation modeling, and debugging complex issues in pre-silicon environments. Requires proficiency in System Verilog and UVM.

Mixed Signal Design Verification Engineer responsible for ensuring the quality and functionality of mixed signal components like PCIE, UCIE, and USB4/Type-C PHYs using methodologies like System Verilog, UVM, and Verilog. The role involves developing verification plans, test benches, simulation models, and conducting root cause analysis. Scripting skills in Python, Perl, or Tcl are required, along with familiarity with standard protocols and EDA tools.

This role focuses on designing and developing power delivery solutions for Intel's platforms, ensuring optimal energy efficiency and performance. Responsibilities include defining, analyzing, and implementing power delivery networks, designing power conversion and management solutions, and collaborating with architects. The role requires expertise in power delivery modeling, PCB design tools, and debugging power systems.

Develops logic design, RTL coding, and simulation for SoC designs, integrating IP blocks. Participates in architecture definition, performs quality checks for power, performance, area, and timing, and ensures design integrity for physical implementation. Reviews verification plans, resolves RTL test failures, and follows secure development practices. Works with IP providers for SoC-level integration and validation, driving quality assurance for IPSoC handoff. Responsible for Xeon SoC integration in the FE domain.

Senior Physical Design Engineer responsible for translating RTL to GDS, performing physical design implementation, and conducting verification and signoff for custom IP and SoC designs. The role involves optimizing designs for power, performance, and area, and participating in methodology development.

Senior Physical Design Engineer at Intel responsible for the physical design of custom IP and SoC designs, impacting products in Client, Data Center, AI, and Automotive sectors. The role involves the full RTL to GDS flow, optimizing power, performance, and area, and technical leadership for SoC/Subsystem implementation.

Intel is seeking a SOC Design Verification Engineer in Bangalore, India, to ensure the functionality, quality, and security of cutting-edge System-on-Chip (SoC) designs. Responsibilities include developing verification plans, test benches, and environments; executing verification plans using emulation and simulation; debugging presilicon issues; collaborating with cross-functional teams; and enhancing verification infrastructure. The role requires proficiency in System Verilog, OVM/UVM, and SoC test environment development, along with strong hardware design knowledge.

This role focuses on SoC Design Verification, developing and executing verification plans, test benches, and environments for Intel's next-generation System-on-Chip (SoC) designs. Responsibilities include functional logic verification, debugging, root cause analysis, and collaborating with cross-functional teams to ensure high-quality SoC designs with a focus on security.

Intel's Hard IP Development Group is seeking an IP Enabling Engineer to join their IO Post Silicon validation debug team. This role involves pre-silicon to post-silicon IP characterization, test plan generation using AI driven tools and Python scripting, SOC board design reviews, and Signal/Power Integrity simulations. The engineer will provide hands-on debug support, identify and resolve IP-related silicon issues, and work closely with SOC customers and IP design teams.

This role is for a Pre and Post Silicon Validation Engineer within Intel's AI Group. The primary focus is on validating the silicon behind Intel's advanced AI platforms, specifically GPUs, Cache, and PCIe technologies in complex AI SoCs. Responsibilities include defining validation strategy, executing pre- and post-silicon validation, debugging complex system-level issues, and developing validation tests and automation. The role requires strong understanding of CPU, GPU, PCIe, and memory management unit architectures, along with expertise in C/C++, Python, and Linux toolchains. While the role is within the AI Group and deals with AI hardware, the core craft is silicon validation, not AI/ML model development.

Analog Circuit Design Engineer role at Intel, focusing on designing, developing, and optimizing high-performance analog circuits for advanced process nodes. Responsibilities include circuit design, simulation, verification, and collaboration with cross-functional teams. Requires expertise in high-speed analog circuit design and proficiency in EDA tools.

Senior Physical Design Engineer specializing in Static Timing Analysis (STA) for Intel's mixed-signal IPs. Responsibilities include timing analysis, optimization, constraint generation, timing rollups, and clock network development to meet performance, power, and functionality goals for next-generation client, server, and ASIC hard-IP portfolios.

Senior Physical Design Engineer responsible for block-level Physical Design execution of Hard-IPs and Testchips, from netlist handoff through GDSII, including floorplanning, placement, CTS, routing, optimization, and ECO closure. Requires experience with industry-standard VLSI flows and tools like Synopsys/Cadence, and scripting in TCL/Python.

This role focuses on the architecture of CPUs, specifically on improving methodologies and infrastructure for power and performance modeling, analysis, and workload bring-up for next-generation client products. The individual will research and drive ideas to enhance SoC power and performance modeling, collaborate with design teams, and analyze bottlenecks to propose solutions.

Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Requires BS/MS with 10+ years of experience in Design verification, System Verilog and OVM/UVM. Experience in validation flow, testbench architecture, verification closure, debug, coverage, simulations, and GLS is essential. Knowledge of DDRPHY validation, DFI/DDR/LPDDR protocols, Python/Perl scripting, Formal Property Verification, and Git is preferred. Exposure to AI tools like GitHub CoPilot is a plus.

Designs and verifies integrated SoCs, ensuring they meet specifications. Develops verification plans, test benches, and environments. Executes verification plans using emulation and simulation, debugs issues, and collaborates with cross-functional teams. Incorporates security and learns from post-silicon feedback to improve future products.

Lab Engineer role at Intel, focusing on technical responsibilities within the Client Computing Group (CCG). Requires a Diploma/ITI/Engineering degree, with preferred qualifications in rework space expertise. This is an on-site, contract employee position in Bangalore, India.

Physical Design Engineer responsible for block-level Physical Design execution of Hard-IPs and Testchips, from netlist handoff through GDSII, including floorplanning, placement, CTS, routing, optimization, and ECO closure. Requires proficiency in scripting and EDA tools.

Physical Design Engineer at Intel responsible for implementing complex mixed-signal IP designs from RTL to GDS for server, client, and graphics microprocessors. This role involves creating manufacturing-ready design databases, conducting power analysis, logic synthesis, place-and-route, verification (FEV, STA, physical verification), and optimizing designs for power, frequency, and area. The engineer will also debug SoC level issues and improve physical design methodologies.

Physical Design Engineer responsible for block-level Physical Design execution of Hard-IPs and Testchips, from RTL/Netlist through GDSII, using established Physical Design methodologies and sign-off practices. Requires proficiency in Netlist-to-GDSII implementation, scripting, and EDA tools.

This role is for an IP Logic Design Engineer at Intel, focusing on designing and optimizing Intellectual Property (IP) blocks for next-generation Custom System-on-Chip (SoC) designs. Responsibilities include RTL coding, simulation, architecture definition, logic optimization for power/performance/area/timing, debugging, and front-end quality checks. The role requires expertise in digital design, RTL coding, System Verilog, low-power design methodologies, and protocols like PCIe and AXI.

Performs physical design implementation of custom IP and SoC designs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, static timing analysis, power/clock distribution, reliability, power/noise analysis, and verification/signoff. Optimizes design for power, frequency, and area, and participates in methodology development and flow automation.

This role focuses on Static Timing Analysis (STA) for next-generation SoCs, ensuring optimal performance and efficiency. Responsibilities include performing timing analysis and optimization, generating and verifying timing constraints, resolving timing violations, conducting timing rollups, developing power-optimized clock networks, and defining methodologies for quality timing models. The role requires collaboration with various engineering teams to achieve clocking balance and power delivery optimization.

Intel's AI SoC organization is seeking an experienced SoC Subsystem Architect to lead the evaluation of architectural trade-offs, define and document micro-architecture for complex SoC IP blocks, and drive silicon bring-up and post-silicon validation for AI hardware. The role involves RTL design, integration, verification, timing constraints, and mentoring junior engineers.

Mixed Signal Design Verification Engineer responsible for ensuring the functionality and performance of mixed signal logic components critical to Intel's success. This role involves developing IP verification plans, test benches, and verification environments, executing detailed verification plans, debugging issues in the presilicon environment, and collaborating with cross-functional teams. The engineer will also maintain and improve functional verification infrastructure, methodologies, and tools.

Designs, develops, and builds analog circuits in advanced process nodes for analog and mixed signal IPs. This includes floorplanning, circuit design, parameter extraction, simulation, test plan creation, and verification. The role focuses on optimizing circuits for power, performance, area, timing, and yield, while collaborating cross-functionally and resolving design issues.

This role focuses on IP Design Verification, ensuring the functional correctness and reliability of intellectual property designs. Responsibilities include developing verification plans, designing test benches, simulating designs, debugging pre-silicon issues, and collaborating with architects and RTL developers. The role requires proficiency in SystemVerilog, experience with complex protocols, and scripting languages like Python or Perl.

RTL Design Engineer for Intel Unified Chassis, focusing on protocol bridges and IP components. Responsibilities include design, implementation, verification, and collaboration with architects and senior engineers. Requires expertise in RTL coding, digital design principles, and hardware description languages like Verilog or VHDL.