Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Currently tracking 56 active AI roles, down 14% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 67 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (4), GenAI Software Solutions Engineer (3), AI Software Engineer Intern (2), Graduate Talent (GenAI Software Solutions Engineer) (2), Middleware Development Engineer (2). Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (51%), agents (27%), application (9%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (20 roles), China (12 roles), Mexico (9 roles), Malaysia (8 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, fine tuning.
In the past 30 days, Intel has posted 43 new AI-related roles. That is a -45% change versus the prior 30 days (78 → 43).
| Title | Stage | AI score |
|---|---|---|
| Senior AI Software Architect - Runtime Intel is seeking a Senior AI Software Architect to lead the development of their neuromorphic AI execution stack for edge and robotic systems. This role involves architecting and optimizing firmware, runtime components, and performance infrastructure, integrating the stack into robotics ecosystems, and providing technical leadership. The position requires extensive experience in low-level systems software for AI accelerators, software architecture, and production-grade software development in C++/Python, with a strong background in AI/deep learning workloads. | ServeShip | 9 |
| Applied Machine Learning Engineer (LLMs & RL) Applied Machine Learning Engineer focused on fine-tuning large language models (LLMs) and Reinforcement Learning (RL). Responsibilities include designing and maintaining post-training pipelines, developing RL environments and reward models, debugging and scaling distributed training, and designing experiments and evaluation metrics. |
| Post-trainAgent |
| 8 |
| GPU Power Architect The role focuses on designing and developing energy-efficient hardware architectures for AI/ML workloads, specifically for GPUs. Responsibilities include building and validating GPU power models, optimizing for performance-per-watt, and developing scalable power analysis flows. The position requires a strong background in computer architecture, digital logic design, and power modeling. | Serve | 8 |
| Principal Engineer: XeSS and Neural Graphics Principal Engineer to drive Intel's XeSS and related AI-based graphics technologies, impacting XeSS Super Resolution, Frame Generation, Neural Rendering, and next-gen AI rendering. The role involves shaping technical direction, driving execution across research, software, hardware, validation, and ecosystem teams, and bringing AI graphics technologies from concept to product. Responsibilities include end-to-end development across model design, datasets, training, visual quality, performance optimization, and product integration, as well as guiding the application of modern AI model architectures to future graphics workloads. | ShipServe | 8 |
| Senior AI SoC Design Engineer This role is for a Senior AI SoC Design Engineer at Intel, focusing on developing hardware for AI applications. The engineer will own the architecture and end-to-end design of complex SoC subsystems, drive RTL design, and collaborate across various engineering disciplines. A strong understanding of AI/ML workloads and their impact on hardware architecture is required, along with expertise in SystemVerilog and microarchitecture. The role involves driving system-level PPA tradeoffs and mentoring senior engineers, contributing to the next-generation SoC and AI architecture roadmap. | Serve | 7 |
| Senior AI Algorithm Engineer in oneDNN Seeking a Senior AI Algorithm Engineer to develop and optimize oneDNN, a critical open-source performance library for deep learning applications, enabling state-of-the-art neural network performance across Intel hardware (CPUs, GPUs). The role involves low-level performance engineering, parallel algorithm development, and contributing to the open-source community. | ServePost-train | 7 |
| Lead Senior Design Engineer – AI SoC Development Lead Senior Design Engineer focused on AI SoC development, responsible for defining, implementing, and validating complex SoC IP blocks and subsystems for AI applications. This role involves architectural leadership, microarchitecture and RTL development, verification collaboration, timing/physical design support, and silicon bring-up, all while ensuring power, performance, and security requirements are met for next-generation AI solutions. | Serve | 7 |
| Image Processing Engineer (C++/Linux) Image Processing Engineer with C++/Linux experience to develop and implement computer vision algorithms for nanometer-scale metrology applications in mask and semiconductor manufacturing. The role involves algorithm development, programming, software tool development, testing, documentation, and user interaction to improve quality control and process development. | Agent | 7 |
| Sr. Security Architect Sr. Security Architect role focused on applying AI-driven tools to enhance security architecture for Client and Data Center SoCs, including firmware and low-level hardware/software. The role involves using AI for vulnerability identification, code analysis, threat modeling, and defining security specifications, aiming to discover risks earlier and more broadly than traditional methods. | Agent | 7 |
| AI Performance Library Architect Software development engineer to work on oneDNN project, a complex cross-platform open-source software project focusing on neural network performance. oneDNN is a critical component of Intel AI strategy, powering key AI applications. Role involves design, development, and maintenance of new functionality in oneDNN to enable performance critical portions of AI workloads, supporting software developers optimizing AI frameworks and workloads for Intel CPUs and GPUs. | Serve | 7 |
| Senior Director, Data & Intelligence Senior Director to lead Enterprise Data & AI Enablement, reporting to VP of AI and Data. Drives strategic roadmap for data and AI capabilities, focusing on robust data foundations for advanced AI applications. Leads cross-functional teams, collaborates with AI leadership, and influences enterprise-wide data and AI strategy. Responsibilities include defining data strategy, overseeing data ingestion and engineering, enabling AI/ML with tooling and environments, developing knowledge products, integrating structured/unstructured data, and designing data models for BI and AI workloads. Also responsible for data governance, quality, literacy, and compliance. Requires proven experience with large-scale data platforms, enterprise applications, data architecture, warehousing, lakehouse technologies, and building AI-ready data foundations. Must demonstrate ability to drive enterprise-wide data strategy, influence senior leadership, build and scale data teams, and partner with AI/ML teams. Experience in regulated industries is preferred. | Data | 7 |
| End to End GPU AI Software Architect This role is for an End-to-End GPU AI Software Architect at Intel, focusing on the entire software stack from firmware to applications to ensure Intel GPU AI software meets product requirements for workloads, performance, and stability. The architect will make key technical design decisions, influence technical direction across the industry, and mentor other technical leaders. | Serve | 7 |
| Development Tools Software Engineer Software Engineer focused on developing validation tools and capabilities, including synthetic content generation for feature validation. Requires experience with AI-assisted development tools and basic prompt engineering, with preferred experience in agentic frameworks and RAG concepts. | Data | 5 |
| Packaging Module Equipment Development Engineer Develops assembly processes and equipment for Intel's future packaging platform technologies, optimizing manufacturing for quality, reliability, and yield. Utilizes AI/ML applications for metrology, processing image data from inspection systems to improve defect detection and minimize false positives. Collaborates with AI experts and automation teams. | — | 5 |
| Analytics and AI Solution Architect This role focuses on developing and implementing cloud-native analytical applications and solutions, with a strong emphasis on leveraging data engineering and cloud platforms. A key aspect involves designing and building pipelines for structured and unstructured data, including the use of Vector databases within a Retrieval Augmented Generative AI architecture. The role also involves applying Lambda architecture, database design, and data modeling, and collaborating on AI/ML infrastructure and big data integrations. | AgentData | 5 |
| Silicon Performance Validation and Characterization Intern Intern role focused on Si performance analysis for network and AI workloads, performance modeling, and architectural tradeoff analysis within the Data Center Group. The role involves assisting with integration planning and collaborating with architects and design engineers to ensure platform scalability and alignment with strategic goals, using state-of-the-art analysis tools. | Serve | 5 |
| WLA Yield Defect Metrology Engineer This role focuses on yield defect metrology engineering within Intel's Advanced Packaging / TD division. The engineer will be responsible for process development, statistical analysis, and identifying root causes of yield limiters by analyzing big data from various sources. This involves developing methods and systems to consolidate and analyze data, applying statistics and machine learning techniques, and creating tools and algorithms for high-volume data analysis to drive yield improvement. The role also involves fault isolation, failure analysis, and ensuring manufacturability through data analysis and collaboration with design teams. While the role uses ML techniques, its primary focus is on yield improvement in semiconductor manufacturing, not on developing AI models as a core craft. | — | 5 |
| Middleware Development Engineer This role focuses on optimizing communication libraries (oneCCL, SHMEM, MPI) for High-Performance Computing (HPC) and AI workloads, specifically identifying and resolving performance bottlenecks in Intel's oneCCL library for AI applications. The engineer will optimize runtime software for distributed systems, ensuring low latency and high bandwidth on Intel GPUs and CPUs, contributing to advancements in scientific discovery and AI systems. | Serve | 5 |
| AI Software Engineering Intern Internship role focused on building AI software stacks, GPU programming, and performance optimization. Contributes to design, development, and optimization of AI software solutions, algorithms, frameworks, and architectures. Assists in implementing and tuning models for performance and accuracy, applied research, and hardware-software integration. May involve creating AI software solutions and system-level deployment for scalable and efficient AI. | Serve | 5 |
| Senior C/C++ Engineer - Media Optimization & Codecs This role focuses on optimizing Intel's hardware features for cloud environments, primarily in the media domain, with potential involvement in AI/ML initiatives. The engineer will design, develop, and debug software, optimize partner stacks, and build scalable cloud-native solutions, collaborating with cross-functional teams and customers to improve performance and enable value from Intel products. | — | 5 |
| Sr. CPU Logic Design Front end Methodology Engineer This role is for a Sr. CPU Logic Design Front end Methodology Engineer at Intel. The engineer will leverage AI tools and methodologies to improve RTL coding and silicon development, provide technical leadership, and contribute to architectural discussions. Responsibilities include developing strategies for RTL development, optimizing logic for power, performance, and timing, and collaborating with other design teams. The role requires experience in silicon development, technical leadership, and driving front-end methodologies with a focus on automation and AI tools. | — | 5 |
| Principal Engineer – Cloud and Datacenter Software Principal Engineer role focused on shaping the future of datacenter and cloud software by engaging with customers, defining optimization opportunities, and influencing technical direction. The role involves architecting solutions, optimizing workloads, and driving technical excellence for Intel platforms. Responsibilities include customer engagement, technical leadership, workload optimization across various environments, mentoring junior leaders, and contributing to open-source communities. The role is critical for shaping next-generation Intel software and silicon codesign. | — | 5 |
| Senior Middleware Development Engineer This role focuses on developing and optimizing communication libraries (Intel SHMEM, MPI, oneCCL) for high-performance computing (HPC) and AI systems, particularly for supercomputers like Aurora. The engineer will work on low-latency, high-bandwidth software for Intel GPUs and CPUs, collaborating with scientists and engineers to advance scientific computing and machine learning. | Serve | 5 |
| Senior Compiler Engineer Senior Compiler Engineer role focused on developing and optimizing compiler software for Intel's GPU programming models, including OpenCL, SYCL, and OpenMP. The role involves designing IR interfaces, implementing optimization algorithms, collaborating with hardware architects, and evaluating workload performance to enhance AI and high-performance computing applications. | — | 2 |
| APTD Manufacturing Technician - Night shift Manufacturing Technician for Intel's Advanced Packaging Technology Development team, focusing on substrate and wafer assembly. Responsibilities include operating and maintaining production equipment, performing preventive maintenance, troubleshooting issues, supporting process improvements, and ensuring quality standards. The role involves data collection, process optimization, and training. | — | 0 |
| Senior CPU RTL Design Engineer Senior CPU RTL Design Engineer responsible for logic design, RTL coding, and simulation for CPU IP blocks. The role involves defining architecture and microarchitecture features, optimizing logic for power, performance, and area, and providing technical leadership to the design team. Experience with Timing Closure, Power Convergence, and OOO execution is required. | — | 0 |
| SoC Integration Engineer Seeking an experienced SoC Integration Engineer to join the Unified Intel Chassis (UIC) team. This role involves working on high-performance Network-on-Chip (NoC) platform solutions, integrating IP blocks into SoC platforms, and collaborating with architecture, IP, and physical design teams to meet power, performance, and area (PPA) targets. The position requires a Bachelor's degree in Electrical Engineering or related field with 6+ years of experience or a Master's degree with 4+ years of experience, specifically in SoC and/or IP design. | — | 0 |
| Senior SoC Power Management Architect This role focuses on defining and developing cutting-edge System-on-Chip (SoC) architectures with emphasis on power management, performance optimization, and energy efficiency for next-generation computing platforms. The Senior SoC Power Management Architect will collaborate across architecture, design, validation, and product teams to deliver scalable solutions from concept through high-volume manufacturing (HVM). Responsibilities include defining and developing SoC power management architecture, maintaining a system-level perspective, evaluating design trade-offs, driving power integration strategies, partnering with hardware and software teams, supporting the full product lifecycle, and analyzing post-silicon power/performance data. | — | 0 |
| Ocotillo Technology Fabrication Process Integration and Yield Engineer Process Integration and Yield Engineer at Intel responsible for analyzing data, identifying root causes of defects and yield issues, and leading continuous improvement projects in semiconductor fabrication. Requires strong statistical analysis and problem-solving skills. | — | 0 |
| OTF Failure Analysis Technician - Night Shift This role is for an OTF Failure Analysis Technician in a semiconductor lab, responsible for operating lab instruments and handling silicon wafers for advanced technology nodes. The job involves sample preparation, operating tools like FIB/PFIB/SEM for cross-sectioning and material analysis, and working from schematics. It requires experience in semiconductor manufacturing or failure analysis tools and emphasizes attention to detail and adaptability in a fast-paced environment. | — | 0 |
| Senior Silicon Photonics TD Reliability Engineer Senior Silicon Photonics TD Reliability Engineer at Intel, focusing on the reliability of silicon photonics technology and devices. Responsibilities include assessing reliability, optimizing processes, conducting experiments, developing new characterization techniques, and collaborating with cross-functional teams to ensure quality and reliability throughout the development lifecycle. The role involves root cause analysis of failures and ensuring smooth transitions from development to high-volume manufacturing. | — | 0 |
| IP Design Verification Engineer This role is for an IP Design Verification Engineer responsible for ensuring the functionality, quality, and reliability of IP designs. Key responsibilities include developing verification plans and test benches, designing and maintaining verification environments, executing verification plans, debugging issues in the pre-silicon environment, and collaborating with cross-functional teams. The role requires a Bachelor's degree in a relevant engineering field and at least 1+ years of experience in IP design verification or a related domain, with specific technical skills in debugging, RTL design concepts, DFV principles, and IP test environments. | — | 0 |
| Construction Engineering Intern Construction Engineering Intern role at Intel, supporting the execution and delivery of semiconductor manufacturing facility projects. Responsibilities include supporting databases, field validation, software testing, design development, and managing engineering content. Requires a Bachelor's degree in a relevant engineering field and strong attention to detail. | — | 0 |
| Senior Technologist, Hybrid Bonding Module Senior Technologist for Die-to-Wafer Hybrid Bonding (HBI) at Intel, focusing on process and equipment development for advanced packaging. The role involves driving improvements in yield, reliability, and defectivity for next-generation hybrid bonding technologies, supporting both development and high-volume manufacturing environments. Requires deep technical expertise in hybrid bonding process or equipment engineering. | — | 0 |
| APTD_SWA Manufacturing Technician Shift 6 Manufacturing Technician for Intel's Advanced Packaging Technology Development: Substrate and Wafer Assembly (APTDSWA) organization. Responsibilities include collecting and evaluating operating data, making adjustments to equipment, performing preventive maintenance, troubleshooting, leading improvement processes, and managing training. | — | 0 |
| Collateral Design and DFM Engineer Intel is seeking a Collateral Design and DFM Lead Engineer to join their Manufacturing Development and Customer Engineering (MDCE) organization. This role focuses on advancing technology nodes from qualification to high-yield production, developing new technologies on mature node infrastructure, and enhancing Design for Manufacturability (DFM) methodologies for improved performance, yield, and ramp-up across diverse product portfolios. The engineer will lead cross-functional teams to define and enhance DFM rules, refine yield tools and flows, and predict and develop rules to avoid design marginalities. | — | 0 |
| NMSi- F11x Dry Etch Module Group Leader Leads a team of module engineers and/or manufacturing operations engineers in the Dry Etch department to support high volume manufacturing, transfer new products, and drive technology development. Focuses on safety, quality, output, and cost, while improving team productivity and efficiency. Requires experience in wafer fabrication engineering, leadership, technical problem-solving, and coaching. | — | 0 |
| Principal Engineer, Design Technology Co-optimization This role focuses on the design and optimization of standard cell libraries for Intel's leading-edge process nodes, involving close collaboration with physical design engineers and EDA partners. The primary goal is to improve cell performance, power, and area to meet internal and external foundry customer needs. It requires a strong technical understanding of advanced semiconductor technology and foundation IP design. | — | 0 |
| Advanced Packaging Technology Development Substrates Module Engineer On-Shift (Nightshift) Module Engineer On Shift (MEOS) provides real-time factory support for equipment, process, and product issues to ensure 24/7 manufacturing operations. Responsibilities include lot movement, responding to process excursions, recovering from equipment errors, lot disposition, new tool enablement, and operational activities. The role requires strong problem-solving, communication, and adaptability in a fast-paced manufacturing environment. Minimum qualifications include a Bachelor's degree in a related engineering or science field with 1+ years of experience, or a Master's degree with 0 years of experience, along with proficiency in statistical data analysis and quality systems. Preferred qualifications include experience with DOE, SPC, semiconductor manufacturing, and metrology tools. | — | 0 |
| Director, SoC Design Engineering Director of SoC Design Engineering responsible for leading functional verification efforts for cutting-edge system-on-chip (SoC) designs, defining and implementing scalable verification methodologies to ensure first-pass silicon success. The role involves architecting verification strategies, developing test benches, leading integration of IPs, and mentoring engineers. | — | 0 |
| APTD_SWA S5 Manufacturing Technician Manufacturing Technician for Intel's Advanced Packaging Technology Development: Substrate and Wafer Assembly (APTDSWA) organization. Responsibilities include collecting and evaluating operating data, making online adjustments to equipment, performing preventive maintenance, troubleshooting issues, supporting production operations, leading improvement processes, and resolving nonstandard events. The role also involves managing training, updating manuals, and participating in safety forums and the Emergency Response Team. Requires adaptability, judgment, and ability to work with general instructions or detailed guidance. | — | 0 |
| Memory Circuit Design Engineer Memory Circuit Design Engineer role focused on developing and optimizing embedded memory designs on Intel advanced CMOS process technologies. Responsibilities include memory pathfinding, PPA optimization, circuit innovation, layout, verification, and validation. | — | 0 |
| Thermal data Analysis Engineer The Thermal Data Analysis Engineer role at Intel focuses on driving thermal design and analysis for GPU and AI accelerators. This involves simulation, experimental work, and cross-functional collaboration to ensure thermal requirements are met for high-performance computing solutions. The role requires expertise in thermal simulation tools, laboratory testing, and applying heat transfer principles to advanced cooling technologies. | — | 0 |
| Design Automation Engineer (TFM/EDA) This role is for a Design Automation Engineer focused on supporting EDA tools and Intel's PDK for external Foundry customers. Responsibilities include installation, maintenance, and technical support of design and compute environments, as well as creating automation scripts to streamline design processes. The role requires experience with front-end and back-end design tools, flows, and methodologies, along with scripting skills in languages like Tcl, Perl, and Python. | — | 0 |
| Silicon Photonics Foundry PDK Design Engineer Seeking a Silicon Photonics (SiP) PDK Design Engineer to join Intel's SPDM team. Responsibilities include creating and documenting pcell designs, design rules, and EDA tool flow automation. The role involves architecting, developing, and validating software solutions for Electronic-Photonic design automation, engaging with partners, and ensuring efficient cloud computing infrastructure. The candidate will lead the development of Design Environment and CI/CD pipelines for hardware and software products. | — | 0 |
| Substrate Quality Engineer Senior Quality and Reliability Engineer to engage with substrate manufacturing suppliers for Intel's EMIB package and assembly solutions. Responsibilities include defining strategies, assessing risks, addressing manufacturing challenges, driving supplier process improvements, and ensuring quality standards. The role involves influencing packaging technology development, partnering with engineering and customer-facing quality teams, responding to customer requirements, and leading quality assessments. A key responsibility is synthesizing data using statistics and machine learning to determine product disposition. | — | 0 |
| APTM NPI Integrator This role focuses on the introduction and transfer of new products and processes within a semiconductor factory environment. The Integrator will coordinate logistics, manage documentation, track progress through the manufacturing flow, and ensure products meet certification requirements before high-volume manufacturing. It involves understanding product lifecycles, fab processing, and post-fab activities, with a strong emphasis on project coordination and issue resolution within the manufacturing process. | — | 0 |
| Yield Development Engineer Yield Development Engineer role focused on semiconductor process development, identifying root cause yield limiters, and driving improvements in manufacturing processes and product reliability. Responsibilities include performing various spectroscopy analyses, providing customer support, assisting with instrument maintenance, and analyzing complex data. Requires a PhD in a STEM field with experience in UHV-based analytical equipment. | — | 0 |
| Ocotillo Technology Fabrication Production Manufacturing Engineer Production Manufacturing Engineer at Intel, focusing on optimizing semiconductor fabrication processes, capacity planning, and factory performance. This role involves driving improvements in cycle time, WIP velocity, output, and quality through data analysis and continuous improvement methodologies in a high-volume manufacturing environment. | — | 0 |
| Memory Circuit Design Engineer Seeking a Memory Circuit Design Engineer to design, develop, and build custom memory circuits (SRAMs, ROMs, Caches) for Intel CPUs and SOCs. Responsibilities include technical readiness, simulation, characterization, PPA optimization, and innovation in memory design on advanced CMOS process technologies. | — | 0 |