Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 56 active AI roles, down 14% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Intel currently has 67 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (4), GenAI Software Solutions Engineer (3), AI Software Engineer Intern (2), Graduate Talent (GenAI Software Solutions Engineer) (2), Middleware Development Engineer (2). Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (51%), agents (27%), application (9%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (20 roles), China (12 roles), Mexico (9 roles), Malaysia (8 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, fine tuning.
In the past 30 days, Intel has posted 43 new AI-related roles. That is a -45% change versus the prior 30 days (78 → 43).
| Title | Stage | AI score |
|---|---|---|
| Design Automation Engineer (TFM/EDA) This role is for a Design Automation Engineer focused on supporting EDA tools and Intel's PDK for external Foundry customers. Responsibilities include installation, maintenance, and technical support of design and compute environments, as well as creating automation scripts to streamline design processes. The role requires experience with front-end and back-end design tools, flows, and methodologies, along with scripting skills in languages like Tcl, Perl, and Python. | — | 0 |
| Silicon Photonics Foundry PDK Design Engineer Seeking a Silicon Photonics (SiP) PDK Design Engineer to join Intel's SPDM team. Responsibilities include creating and documenting pcell designs, design rules, and EDA tool flow automation. The role involves architecting, developing, and validating software solutions for Electronic-Photonic design automation, engaging with partners, and ensuring efficient cloud computing infrastructure. The candidate will lead the development of Design Environment and CI/CD pipelines for hardware and software products. | — |
| 0 |
| Substrate Quality Engineer Senior Quality and Reliability Engineer to engage with substrate manufacturing suppliers for Intel's EMIB package and assembly solutions. Responsibilities include defining strategies, assessing risks, addressing manufacturing challenges, driving supplier process improvements, and ensuring quality standards. The role involves influencing packaging technology development, partnering with engineering and customer-facing quality teams, responding to customer requirements, and leading quality assessments. A key responsibility is synthesizing data using statistics and machine learning to determine product disposition. | — | 0 |
| Intel Foundry Strategic Planning Demand Analyst This role is responsible for demand planning and forecasting within Intel Foundry's strategic planning team. It involves collecting, analyzing, and reporting demand data, identifying trends, developing strategies to meet demand, and managing the long-range strategic business plan. The analyst will also run demand solves for mid-term and long-term requirement scenarios, integrating various signals and staying updated on industry trends. | — | 0 |
| APTM NPI Integrator This role focuses on the introduction and transfer of new products and processes within a semiconductor factory environment. The Integrator will coordinate logistics, manage documentation, track progress through the manufacturing flow, and ensure products meet certification requirements before high-volume manufacturing. It involves understanding product lifecycles, fab processing, and post-fab activities, with a strong emphasis on project coordination and issue resolution within the manufacturing process. | — | 0 |
| Yield Development Engineer Yield Development Engineer role focused on semiconductor process development, identifying root cause yield limiters, and driving improvements in manufacturing processes and product reliability. Responsibilities include performing various spectroscopy analyses, providing customer support, assisting with instrument maintenance, and analyzing complex data. Requires a PhD in a STEM field with experience in UHV-based analytical equipment. | — | 0 |
| Ocotillo Technology Fabrication Production Manufacturing Engineer Production Manufacturing Engineer at Intel, focusing on optimizing semiconductor fabrication processes, capacity planning, and factory performance. This role involves driving improvements in cycle time, WIP velocity, output, and quality through data analysis and continuous improvement methodologies in a high-volume manufacturing environment. | — | 0 |
| Memory Circuit Design Engineer Seeking a Memory Circuit Design Engineer to design, develop, and build custom memory circuits (SRAMs, ROMs, Caches) for Intel CPUs and SOCs. Responsibilities include technical readiness, simulation, characterization, PPA optimization, and innovation in memory design on advanced CMOS process technologies. | — | 0 |
| Substrate Manufacturing Technician Shift 7 Manufacturing Technician role at Intel focused on semiconductor substrate and wafer assembly. Responsibilities include equipment operations, maintenance, calibration, process optimization, quality control, and training. Requires adaptability, strong judgment, leadership, and problem-solving skills. Open to candidates with a STEM degree or relevant manufacturing experience. | — | 0 |
| Analog Circuit Design Engineer Graduate Intern Internship role focused on the design, simulation, and verification of digital and/or analog circuits for Intel's next-generation technologies. Responsibilities include schematic entry, timing analysis, noise glitch analysis, debugging, and utilizing EDA tools. Requires pursuit of a Master's or Ph.D. in Electrical/Computer/Software Engineering, Computer Science, or related field, with knowledge of circuit design principles, EDA tools, CMOS technologies, and semiconductor device physics. | — | 0 |
| Mixed Signal Design Verification Engineer This role involves performing functional verification of mixed-signal logic components, including analog behavioral modeling, to ensure design specifications are met. Responsibilities include developing IP verification plans, test benches, and verification environments, executing verification plans, running system simulation models, analyzing power and timing, debugging issues, and collaborating with digital and analog architects, RTL developers, and physical design teams. The role also requires maintaining and improving verification infrastructure and methodology. | — | 0 |
| Senior Thermal Architect - Intel Contract Employee This role focuses on the thermal architecture and cooling solutions for complex electronic systems, including AI/HPC platforms. The Senior Thermal Architect will define thermal budgets, lead CFD/FEA simulations, and collaborate with silicon and power teams to optimize thermal performance. Responsibilities include specifying cooling components, leading lab characterization, and mentoring junior engineers. The role requires a BS in Mechanical Engineering and 9+ years of thermal design experience, with proficiency in CFD tools and lab instrumentation. Preferred qualifications include experience with advanced cooling techniques and high-power AI/GPU/CPU thermal design. | — | 0 |
| Packaging Module Development Engineer Develops and optimizes semiconductor packaging technologies, focusing on First Level Interconnects and assembly processes for future platforms. This role involves leading equipment development, managing projects, and collaborating with cross-functional teams to ensure quality, reliability, and manufacturability for high-volume production. | — | 0 |
| Package Assembly Low Yield Analysis Engineer on Shift Engineer responsible for technical functions such as design, test, checkout, modifications, and characterization of assembly technologies to root cause yield loss and in-line failures in semiconductor package assembly. This role involves hands-on lab work, data analysis, and developing failure analysis techniques. Requires a degree in a relevant engineering field and experience with characterization or fault isolation tools. | — | 0 |
| Infra and DevOps Intern Intern role focused on supporting and optimizing Engineering Computing infrastructure and platforms, including server support, automation, monitoring, and deployment workflows. The role involves scripting, source control, and troubleshooting within a Windows Server environment. | — | 0 |
| ADCE Packaging Design Architect Drives end-to-end development for substrate design from concept through tape out and implements physical layout and routing of the package design. Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs. Works closely with silicon and hardware teams to optimize silicon-package-board performance and pinout. Defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves DRCs to optimize package design. Completes documentation and collateral into the product lifecycle management system of record. | — | 0 |
| Supply Chain Engineer Supply Chain Engineer responsible for incorporating process and quality improvements in Intel's supply chain and logistics strategy, supporting product ramps by defining next-generation methodology capabilities, exploring emerging technology, and contributing to future technology definition. The role involves establishing control standards, monitoring KPIs, driving root cause analysis for supplier-related equipment installation and qualification, and managing supplier improvements on quality, reliability, yield, and cost. Key responsibilities include owning CEID standard durations, tracking supplier performance, managing escalations, leading supplier management meetings, driving MQI activities, and owning strategic IQ labor planning. | — | 0 |
| Advanced Packaging Supplier Technology Development Program Manager The Advanced Packaging Substrate Integration Team is seeking a Program Manager to oversee on-time supplier capacity expansion for advanced heterogeneous packaging technology (EMIB-T). This role involves qualifying new process tools, supplier lines, and factories to meet foundry customer demand. Responsibilities include scoping, planning, CapEx project execution, capability transfer from internal lines to suppliers, and regular management updates. The position requires strong project management, technical risk assessment, problem-solving, and supplier/stakeholder management skills, with extensive interaction with supplier and internal teams, including international travel. | — | 0 |
| FCO Strategic/Development Functional Area Industrial Engineer This role is for an Industrial Engineer focused on factory capacity planning, capital equipment planning, and site space optimization within Intel's manufacturing operations. The role involves analyzing business data, developing data-driven models, forecasting build plans, and collaborating with cross-functional teams to drive manufacturing strategies and operational excellence. While the company mentions "AI everywhere" and "AI product development" in a general context, the core responsibilities of this role are centered on traditional industrial engineering principles for manufacturing and capacity planning, not on building or directly working with AI/ML models or systems. | — | 0 |
| OTF IFA AMHS Equipment Technician This role involves performing electrical and mechanical troubleshooting, repair, and maintenance of manufacturing equipment within Intel's Automated Material Handling System (AMHS) in a cleanroom environment. The technician will also support engineering teams with experiments and data collection, and collaborate during factory ramps. | — | 0 |
| Product Development Engineer Product Development Engineer in the Parametric Test area supporting electric test programs for discrete devices to measure and improve performance and reliability of new process technologies and designs. Responsibilities include defining test content, validating designs, developing test programs, validating results on silicon, and improving testing methods and systems. Also involves defining high volume systems and meeting capacity constraints. | — | 0 |
| Packaging Module Development Engineer Develop, qualify, and optimize semiconductor packaging equipment and processes. Apply statistical methods (DOE, SPC) to analyze process performance and drive continuous improvement. Design and execute experiments to validate packaging technologies under environmental stress conditions. Collaborate cross-functionally with design, manufacturing, and suppliers. Define equipment specifications and partner with vendors. Identify and resolve packaging-related reliability issues using data-driven approaches and failure analysis techniques. Lead technical problem-solving efforts and contribute to process innovation initiatives. | — | 0 |
| Foundry Strategic Industrial Engineer Intel Foundry is seeking a Strategic/Development Industrial Engineer to coordinate data, systems, decision analysis, business processes, and modeling with a focus on capacity and cost. The role involves driving strategies to enhance manufacturing and operational capabilities, forecasting, designing plans aligned with market trends, and empowering stakeholders with data-driven decisions. Responsibilities include developing and maintaining data systems, models, and business processes, providing strategic guidance through data analysis, facilitating business processes, coordinating scenario-based analysis, developing financial models, and defining long-range capacity strategy. | — | 0 |
| Physical Design Engineer- Foundry Services Physical Design Engineer for Intel Foundry Services, focusing on Si Interposer and Bridge designs. Responsibilities include full physical design flow (floor planning, place and route, verification, analysis), optimization for performance/power/area, and methodology development. Requires a Bachelor's or Master's degree in Electrical Engineering or related field with significant experience in EDA tools and physical design aspects. | — | 0 |
| Mask Manufacturing Technician This role involves performing manufacturing and assembly tasks in a production process, ensuring products meet industry standards and customer specifications. Responsibilities include operating equipment, collecting and evaluating operating data for process optimization, maintaining production efficiency, setting up and operating production equipment, supporting installation and maintenance of equipment, driving utilization of automated systems, producing product that meets output requirements, supporting process improvements, troubleshooting production line issues, and conducting quality checks on raw materials and final products. | — | 0 |
| CPU Core Senior Physical Design Engineer Senior Physical Design Engineer for CPU core development, responsible for the full physical design flow from RTL to GDS, including synthesis, place and route, timing analysis, power analysis, and verification. Collaborates with other engineering teams and EDA vendors to optimize CPU design for power, frequency, and area. | — | 0 |
| Mechanical Project Engineer Mechanical Project Engineer for Intel's Global Construction Engineering organization, responsible for the design and engineering of semiconductor manufacturing facilities. This role involves assessing project feasibility, developing scope, providing technical guidance to supply chain partners, and ensuring cost management for mechanical systems like HVAC, chillers, boilers, and process vacuum systems. The position requires collaboration across disciplines and a focus on safety and innovation within the semiconductor industry. | — | 0 |
| Module Development Engineer This role focuses on the development and optimization of advanced semiconductor manufacturing processes, including material selection, parameter adjustments, equipment metrology, and system design. It involves feasibility studies, process technology development, and collaboration with suppliers to integrate new technologies into manufacturing. The role requires a PhD in a STEM discipline and fundamental knowledge of plasma physics, surface reactions, thin film processes, and semiconductor materials. | — | 0 |
| Ethernet Product Manager Product Manager for Intel's Ethernet controllers and adapters, focusing on defining software requirements, managing the product lifecycle, conducting market research, and driving adoption. Requires strong technical background, market insight, and collaboration with engineering, marketing, and sales. | — | 0 |
| IA Core Post Silicon Validation Engineer Intel is seeking a Post Silicon Validation Engineer for their All Cores Engineering (ACE) Group. This role focuses on core level validation of leading CPU products for Xeon Server products. Responsibilities include developing validation plans, powering on new systems, validating product features, and debugging functional bugs. The role requires expertise in CPU Post-Si debug and validation, test generators, and various validation techniques. | — | 0 |
| Post-silicon Validation and Debug Engineer This role focuses on post-silicon validation and debug engineering for Intel's System-on-Chip (SoC) products, ensuring seamless performance by working at the intersection of hardware, firmware, and software. Responsibilities include performing low-level debug, developing validation plans, implementing debug techniques, conducting root cause analysis, and collaborating with cross-disciplinary teams. | — | 0 |
| Principal Engineer, Hybrid Bonding Module This Principal Engineer role focuses on defining and scaling next-generation advanced packaging technologies, specifically die-to-wafer hybrid bonding (HBI), for high-performance computing, AI, and chiplet architectures. The role involves driving hybrid bonding capability from platform development through high-volume manufacturing, focusing on equipment and process development, yield and reliability improvement, and platform innovation. | — | 0 |
| FCO Functional Area Industrial Engineer This role is for a Factory Capacity Optimization (FCO) Functional Area Industrial Engineer focused on Assembly. The candidate will design, develop, validate, and deploy models to solve complex manufacturing and supply chain problems. Responsibilities include identifying risks and opportunities for toolset roadmaps, defining long-range capacity strategy, forecasting build plans, leveraging data analysis for insights, creating capacity requirements, developing execution plans, monitoring toolset performance, and investigating/designing production capacity models and data systems. The role also involves developing mathematical equipment run rate models and supporting ramp/end-of-life plans. | — | 0 |
| Supply Chain Engineer Supply Chain Engineer role at Intel focused on optimizing semiconductor manufacturing processes, managing supplier quality, and driving cost control and yield improvements. Requires experience in semiconductor factory operations, supply chain engineering, or supplier management, with a strong emphasis on root cause analysis and performance tracking. | — | 0 |
| Software Enabling and Optimization Engineer This role focuses on enabling next-generation programmable Infrastructure Processing Units (IPUs) for Intel's Networking Solutions Group (NSG) by working with lead customers. The engineer will define and develop IPU solutions, perform system-level testing, collaborate with engineering teams and customers for debugging, create technical collaterals, and engage with industry technologists to evaluate feasibility and influence engineering direction. The role requires strong programming skills in Python, experience with build tools, and knowledge of Linux networking stacks. | — | 0 |
| Mixed Signal Logic Design Engineer This role focuses on the design of mixed-signal logic for high-speed IP at Intel. Responsibilities include developing architecture and microarchitecture specifications, implementing designs in RTL, behavioral modeling, simulation, debugging, and supporting physical design and validation teams. The role requires experience with digital design concepts, SystemVerilog, computer architecture, and analog/mixed-signal design. Experience with AI tools for productivity is a plus. | — | 0 |
| Senior Mixed Signal IP Enablement and Debug Engineer This role focuses on the integration and debug of Mixed Signal Intellectual Property (IP) for Intel's Hard IP Development Group. Responsibilities include partnering with customers and design teams, developing test plans using AI-driven tools and scripting, conducting design reviews, performing simulations, leading silicon validation and debug, and driving root cause analysis for IP-related issues. The role requires experience in IP integration, pre-silicon verification, post-silicon validation, and debug of serial or parallel IOs, along with lab hardware and software experience. | — | 0 |
| Senior Staff Mixed Signal IP Enablement and Debug Engineer This role focuses on enabling and debugging mixed-signal IP (Intellectual Property) for Intel's Hard IP Development Group. Responsibilities include customer support, IP documentation, integration and debug support, developing test plans using AI-driven tools and scripting, conducting design reviews, and performing signal/power integrity simulations. The role also involves silicon validation, leading issue identification and resolution, and root cause analysis. The ideal candidate will have experience in IP integration, pre-silicon verification, post-silicon validation, and debug of serial or parallel IOs, with strong lab hardware/software skills and experience with test equipment. | — | 0 |
| MDM Software Application Development Engineer This role is for an MDM Software Application Development Engineer at Intel, focusing on designing, configuring, and developing SAP MDG and S4 HANA solutions. Responsibilities include defining software application solutions, recommending design choices for manageability and scalability, identifying business requirements, configuring systems, collaborating with stakeholders, performing pathfinding, and troubleshooting production issues. The role also involves acting as a technical lead for subsystems and managing projects. The ideal candidate will have extensive experience with SAP MDM and S4 HANA, ABAP, SAP Fiori, and SQL queries, with preferred experience in data cleansing, governance, and integration. | — | 0 |
| Mask Manufacturing Technician This role involves performing manufacturing and assembly tasks, operating and optimizing production equipment, conducting quality control evaluations, and supporting new product development and process improvements in a semiconductor manufacturing environment. The technician will ensure products meet industry standards and customer specifications, maintain production logs, and collaborate with management and engineering teams. | — | 0 |
| Identity Architect Seeking an Identity Architect to design and build secure classified products for US Government operations, focusing on end-to-end client identity solution architectures using hardware capabilities and supporting engineering system specifications. Requires strong knowledge of identity protocols (OpenID Connect, OAuth, FIDO, SAML), biometrics, authentication, and authorization solutions, with an understanding of Intel CPU architecture. | — | 0 |
| Power and Performance Design Engineer Intel is seeking a Power and Performance Design Engineer to design and optimize IPs and SoCs, focusing on power efficiency, thermal management, and performance balance. Responsibilities include developing tools for performance analysis, collaborating with cross-functional teams, and providing recommendations for future architectures. Requires a Bachelor's degree with 9+ years of experience or equivalent. | — | 0 |
| SoC Power and Performance Architect Develops and drives end-to-end SoC architecture, including firmware, hardware, and platform specifications for highly optimized, modular, and scalable SoCs. Drives SoC functionality, connectivity, configuration, performance, timing, power, and area goals. Evaluates feasibility tradeoffs and explores new approaches for SoC. Develops tests, test plans, and testing infrastructure for new architectures/features for SoC, performs functional modeling simulations, and conducts analysis of test results using advanced statistics and data predictions for benchmarking performance and determining areas for improvement. Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints. Reviews, challenges, and influences cross-functional roadmaps and defines technology targets for future SoCs. Collaborates with architects, design engineers, system engineers, and verification engineers to improve the overall design of SoC and overcome constraints. | — | 0 |
| LTD Process Development Integration Engineer Process Integration Development Engineer at Intel, focusing on advancing semiconductor manufacturing processes for Logic Technology Development (LTD). Responsibilities include leading quality event responses, performing statistical analysis on fab and E-test data, monitoring yield, conducting root cause analyses, and developing process targeting strategies to optimize product performance and yield. Requires a Bachelor's degree in a relevant STEM field and experience in semiconductor industry, statistical data analysis, and root cause analysis. | — | 0 |
| New Mexico Manufacturing Technician Internship Internship role focused on manufacturing operations within Intel's Advanced Packaging Technology Manufacturing (APTM) plant. Responsibilities include equipment setup, monitoring production processes, quality checks, and assisting with troubleshooting and optimization. The role involves hands-on experience in a fast-paced, challenging environment supporting wafer movement and production goals, with a focus on learning and skill development. | — | 0 |
| CPU Physical Design Engineer This role is for a CPU Physical Design Engineer at Intel. The engineer will be responsible for the physical design implementation of custom CPU designs from RTL to GDS, including synthesis, place and route, clock tree synthesis, static timing analysis, and power/clock distribution. The role involves verification and signoff, optimization for power, frequency, and area, and working with EDA vendors to enhance tool capabilities. While the company works in AI, this specific role focuses on the hardware design of CPUs that may be used in AI applications, rather than the AI/ML development itself. | — | 0 |
| Identity Security - PKI Engineer The Identity Security - PKI Engineer role at Intel focuses on designing, deploying, and managing enterprise-grade Public Key Infrastructure (PKI) solutions. This involves leading certificate lifecycle management, automating PKI tasks, integrating PKI with various platforms, and enforcing security policies. The role requires a Bachelor's or Master's degree and relevant experience in PKI integration, X.509 certificates, and key management standards. A US Government Security Clearance is required. | — | 0 |
| CPU Physical Design Engineer This role involves the physical design implementation of custom CPU designs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power/noise analysis. It also includes verification and signoff, working with EDA vendors, and optimizing CPU designs for power, frequency, and area. The role requires collaboration with various engineering teams and participation in methodology improvements. | — | 0 |
| Senior DSP Algorithm Engineer Senior DSP Algorithm Engineer to design and develop advanced Digital Signal Processing algorithms in MATLAB for wireless communications and defense applications. Collaborate with cross-functional teams, create technical documentation, partner with customers, research innovative approaches, and conduct competitive benchmarking. | — | 0 |
| CPU Physical Design Engineer This role involves the physical design implementation of custom CPU designs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power/noise analysis. It also includes verification and signoff, working with EDA vendors, and optimizing CPU design for power, frequency, and area. | — | 0 |