Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Currently tracking 56 active AI roles, down 14% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 67 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (4), GenAI Software Solutions Engineer (3), AI Software Engineer Intern (2), Graduate Talent (GenAI Software Solutions Engineer) (2), Middleware Development Engineer (2). Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (51%), agents (27%), application (9%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (20 roles), China (12 roles), Mexico (9 roles), Malaysia (8 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, fine tuning.
In the past 30 days, Intel has posted 43 new AI-related roles. That is a -45% change versus the prior 30 days (78 → 43).
| Title | Stage | AI score |
|---|---|---|
| Enterprise Systems Analyst This role is for an Enterprise Systems Analyst at Intel, focusing on supply chain transformation and the internal foundry model. The analyst will work with Windchill PLM, gather requirements, document processes, develop training, and support end-users. The role involves data and system management, and integration with other enterprise systems. While the company mentions AI, this specific role is focused on PLM and supply chain systems, not direct AI/ML model development or deployment. | — | 0 |
| Standard Cell Library Engineer This role focuses on the development and validation of tools, flows, and collaterals for standard cell library reliability, including electromigration, thermal effects, and voltage drop. Responsibilities involve workflow optimization, vendor and foundry engagement, and documentation/collateral generation and validation. | — | 0 |
| GPU Software Development Engineer This role focuses on graphics driver/application validation and debug, integrating upcoming graphics features, triaging failures, and developing debug tools to improve graphics validation efficiency. It involves scaling across display, media, 3D, compute, and power conservation components, and enabling new features for AI domains to improve functionality and performance on graphics products. |
| — |
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| Mixed Signal Logic Design Engineer Develops logic design, RTL coding, and simulation for mixed signal and/or highspeed IPs for integration in full chip designs. Participates in architecture and microarchitecture definition, applies strategies for mixed signal designs, writes RTL, and optimizes logic to meet power, performance, area, and timing goals. Reviews verification plans, resolves failing RTL tests, and supports SoC customers for IP block integration. | — | 0 |
| Post-silicon Validation and Debug Engineer This role is for a Post-Silicon Validation Engineer at Intel, focusing on ensuring the quality and functionality of CPU products for laptops, desktops, and gaming systems. Responsibilities include developing and executing validation plans, designing and debugging tests, analyzing issues, leading debug task forces, driving automation, and mentoring junior engineers. Requires experience in post-silicon validation, CPU/SOC architecture, and scripting languages. | — | 0 |
| CPU Memory Design Engineer This role focuses on designing, developing, and building custom memory circuits (SRAMs, ROMs, register files, caches) for Intel CPUs and SOCs. Responsibilities include technical readiness, circuit design, characterization, simulations, PPA optimization, and methodology definition within advanced CMOS process technologies. | — | 0 |
| CPU Memory Design Engineer CPU Memory Design Engineer responsible for designing, developing, and building full-custom and compiler-based SRAMs, Large Signal Arrays, ROMs, custom memories, digital circuits, and Caches for Intel CPUs and SOCs. Involves technical readiness, circuit design, characterization, simulations, cache design, critical path simulations, PPA optimization, bit-cell and periphery IC design, automation, IP design, and methodology definition. | — | 0 |
| Packaging Module Development Engineer Develops and optimizes semiconductor packaging assembly processes and equipment for next-generation technologies, focusing on quality, reliability, and manufacturability. | — | 0 |
| LTD Frame Automation Software Engineer Software Engineer role focused on designing, developing, testing, and debugging software tools, flows, and methodologies for design automation in the semiconductor industry. Responsibilities include capturing requirements, writing functional and test code, automating build/deployment, and performing testing. The role also involves designing web-based interfaces for tool configuration and control, and supporting Linux EDA tool infrastructure. | — | 0 |
| Manufacturing Equipment Technician (MTE) This role is for a Manufacturing Equipment Technician at Intel, focusing on supporting and improving semiconductor manufacturing equipment in a cleanroom environment. Responsibilities include troubleshooting, repair, setup, calibration, and preventive maintenance of electromechanical equipment, particularly in wet chemistry, plating, and dry high-vacuum systems. The role requires strong problem-solving skills, collaboration with engineering teams, and documentation of maintenance activities. A STEM degree, technical certification, or related experience is required. | — | 0 |
| eCOTS Product Owner Product Owner for eCOTS solutions in a semiconductor and integrated hardware/software environment, aligning with USG and Defense Industrial Base requirements. Responsibilities include backlog prioritization, user story definition, Agile delivery, and roadmap development. Requires experience in product ownership, Agile methodologies, and cross-functional collaboration, with a preference for semiconductor or technical product environments and USG/DIB experience. | — | 0 |
| Packaging Module Development Engineer Develops and optimizes assembly processes and equipment for semiconductor packaging, focusing on manufacturing efficiency, quality, reliability, and cost. This role involves applying experimental design and data analysis to innovate solutions for Intel's future packaging technologies, ensuring manufacturability, and establishing material specifications. | — | 0 |
| Intel Products Supply Chain Business Architect Intel is seeking an experienced Business Architect for their Enterprise Customer Fulfillment and Integration organization. This role focuses on enabling the integration of new products and businesses into Intel's supply chain, defining requirements, and leading integration teams. The ideal candidate will have strong project management, requirements definition, analytical thinking, business operations, and communication skills, with experience in supply chain software and data analytics. | — | 0 |
| Ocotillo Technology Fabrication Sh6 Production Line Engineer Production Line Engineer responsible for managing shift loop operations to meet quality and output goals in a semiconductor fabrication environment. Key responsibilities include strategic WIP management, optimizing loop performance, coordinating maintenance, gathering tool status, documenting utilization gaps, and understanding root causes for missed goals. Requires strong analytical, communication, and problem-solving skills, with experience in manufacturing or semiconductor operations. | — | 0 |
| Mechanical Design Engineer – Semiconductor Packaging Mechanical Design Engineer responsible for designing Tape and Reel packaging, substrates, heat spreaders, and other mechanical components for semiconductor packaging and assembly. Requires CAD skills and collaboration with cross-functional teams. | — | 0 |
| Assembly Packaging Technical Integrator - Intel Foundry Services MAG Product Packaging Engineer responsible for designing, developing, and qualifying packaging solutions for Intel's products, ensuring they meet product, regulatory, and environmental requirements. This role involves collaboration with manufacturing, logistics, and supply chain teams, identifying cost-saving measures, conducting risk analyses, and evaluating vendors. Requires technical knowledge in semiconductor packaging, assembly, and reliability analysis. | — | 0 |
| Engineering Planning Analyst This role is for an Engineering Planning Analyst at Intel, focused on managing the transition of new products from development to high-volume manufacturing. Responsibilities include coordinating startup activities, developing supply plans, monitoring product flow, creating forecasts, performing scenario analyses, driving product setup (BOM, routing), aligning demand with supply, analyzing manufacturing risks, and applying analytics for supply strategies. The role requires proficiency in data analysis tools like Excel and Power BI, experience in demand/supply planning or supply chain management, and skills in supply chain modeling and optimization. | — | 0 |
| Process Integration Development Engineer This role involves characterizing semiconductor nano-devices using advanced transmission electron microscopy (TEM) to support technology development, process development, and process integration. The engineer will perform imaging and analysis using TEM, EELS, EDX, and 4D STEM, with a focus on improving time-to-information-return for critical manufacturing processes. | — | 0 |
| Module Development Engineer Drives technology development and enablement for semiconductor manufacturing, focusing on process integration, equipment solutions, and feasibility studies for new product designs. The role involves leading the design and development of manufacturing processes, including material selection, parameter optimization, and equipment metrology, with a strong emphasis on dry etch semiconductor manufacturing. Responsibilities include performing pathfinding activities, recommending modifications to operating equipment, partnering with suppliers, and conducting process technology feasibility studies. The role requires expertise in plasma etch fundamentals, statistical analysis, and DOE methodologies, with a demonstrated record of improving yield, reliability, performance, or manufacturability for advanced technology nodes. | — | 0 |
| Module Development Engineer Drives technology development and enablement for semiconductor manufacturing, focusing on process integration, equipment solutions, and feasibility studies. Leads design and development of manufacturing processes, including material selection, parameter optimization, and equipment metrology. Performs pathfinding activities for process and hardware development, enabling innovative device architectures and developing roadmaps. Recommends and implements modifications to operating equipment to improve production efficiency and output. Partners with suppliers for technology enablement. Requires PhD/Master's/Bachelor's in a semiconductor-related STEM field with relevant experience in dry etch semiconductor processing, plasma etch fundamentals, process development, optimization, and characterization. Proficiency in statistical data analysis and DOE tools is expected. | — | 0 |
| Intel Foundry Module Development Engineer This role focuses on developing and manufacturing advanced semiconductor process technologies, including designing, executing, and analyzing experiments to meet engineering specifications. It involves integrating manufacturing steps, ramping to production volumes, and transferring technology to manufacturing counterparts. The role requires a Ph.D. in a relevant STEM field and significant semiconductor industry experience, with specific expertise in overlay development and understanding of modern semiconductor manufacturing processes. | — | 0 |
| Intel Foundry Lithography Module Development Engineer Develops and executes lithography manufacturing processes for semiconductor devices, ensuring manufacturing viability and high-volume production. This role involves designing experiments, analyzing data, collaborating with partners and suppliers, and transferring technology to other factories. | — | 0 |
| Intel Foundry Lithography Module Engineer This role focuses on the development and execution of lithography manufacturing processes for semiconductor devices. Responsibilities include designing and analyzing experiments, developing intellectual property, collaborating with equipment suppliers, installing and qualifying High Volume Manufacturing (HVM) capacity, and transferring technology to other Intel factories. It is an entry-level position requiring a Master's degree in a relevant science or engineering field and some experimental lab work. | — | 0 |
| Ocotillo Technology Fabrication Module Equipment Technician Module Equipment Technician role at Intel focused on maintaining and optimizing manufacturing equipment for semiconductor fabrication, specifically in Dry Etch, Diffusion, and Thin Films processes. Responsibilities include equipment maintenance, repair, troubleshooting, and defect reduction. Requires STEM education or equivalent experience and strong problem-solving skills. | — | 0 |
| Physical Design Engineer for Core IP Physical Design Engineer for Core IP at Intel, responsible for the implementation of custom CPU designs from RTL to GDS, including synthesis, place and route, timing analysis, and verification. The role involves optimizing CPU designs for power, frequency, and area, and working with EDA vendors to enhance tool capabilities. | — | 0 |
| Package Power Integrity Intern Internship role focused on Power Integrity/Delivery Electrical analysis for IC packages, involving extraction, analysis, and optimization of high-performance interfaces. Requires Masters/PhD in Electrical Engineering and experience with simulation tools. | — | 0 |
| WLA Yield Defect Metrology Engineer Engineer focused on identifying root cause yield limiters in semiconductor manufacturing through statistical analysis, big data consolidation, and machine learning techniques. Develops methods and tools for high-volume data analysis to drive yield improvement actions and ensure manufacturability. | — | 0 |
| Load Balancer Network Engineer Network Security Engineer role focused on designing, architecting, and building secure classified network products for USG operations, requiring experience with load balancing, network security infrastructure, and hardening systems in accordance with federal guidance. Requires active Top Secret clearance. | — | 0 |
| Identity Security - PKI Engineer This role focuses on designing, deploying, and managing Public Key Infrastructure (PKI) solutions, including certificate lifecycle management and automation. It involves collaboration with security, infrastructure, and DevOps teams, and ensuring compliance with internal and regulatory requirements. The position requires a Bachelor's or Master's degree in a relevant field and experience with PKI integration, X.509 certificates, and related standards. | — | 0 |
| Senior Full Chip Physical Design Integration Lead This role is for a Senior Full Chip Physical Design Integration Lead at Intel. The primary responsibility is to drive the physical design implementation of custom IP and SoC designs, transforming RTL to GDS databases for manufacturing. This involves optimizing power, frequency, and area metrics, and conducting verification and signoff activities. The role also includes enhancing physical design methodologies and collaborating with cross-functional teams. | — | 0 |
| Senior AI SoC Design Engineer This role is for a Senior AI SoC Design Engineer at Intel, focusing on defining and implementing RTL for SoC blocks, collaborating with IP providers, and ensuring design quality for next-generation computing platforms. The role requires strong RTL design, microarchitecture, and SoC architecture skills, with a preference for understanding AI models and their impact on hardware. | — | 0 |
| Senior AI SoC Design Engineer This role is for a Senior AI SoC Design Engineer at Intel, focusing on defining and implementing RTL for SoC blocks, collaborating with IP providers, and ensuring design quality for next-generation computing platforms. The role requires strong RTL design, microarchitecture, and SoC architecture skills, with a preference for understanding AI models and their impact on hardware. | — | 0 |
| APTD Substrates Factory Engineer Factory Engineer role focused on troubleshooting and maintaining facilities systems (e.g., Exhaust, Drains, PCW) and leading projects related to factory safety, quality, and upgrades within Intel's Advanced Packaging Technology Development Substrates organization. Requires a Bachelor's or Master's degree in a relevant engineering discipline and experience in semiconductor manufacturing or equipment engineering. | — | 0 |
| Facilities Engineer Instrumentation and Controls - Intel Contract Employee Facilities Engineer focused on instrumentation and controls for industrial automation platforms (GE Cimplicity, Rockwell Automation Control Logix PLC) in a manufacturing/facility setting. Responsibilities include system design, maintenance, troubleshooting, project management, and ensuring operational efficiency and compliance. | — | 0 |
| Senior EDA Tools Hardware Engineer This role focuses on designing, implementing, and enabling next-generation hardware design tools, flows, and methodologies for advanced technology nodes at Intel. The engineer will analyze and optimize methodologies for power, performance, area, and efficiency, build platforms and scripts for design automation, and collaborate with EDA vendors to test and adopt new tools. The role requires experience in EDA tools, physical design, digital design, and verification. | — | 0 |
| Path Tracing/ML Research Engineer This role focuses on designing, developing, and optimizing software for ray tracing, including improving customer designs and optimizing workloads for benchmarks and performance analysis. While it mentions AI-related math concepts, the core craft is software engineering for graphics and simulation, not AI model development. | — | 0 |
| OTF IFA AMHS - S6 Group Leader Lead a team of technicians supporting Automated Material Handling Systems (AMHS) in Intel's manufacturing factories, ensuring reliability, availability, and performance. This role involves hands-on operational leadership, daily execution, staffing, service quality, continuous improvement, and fostering a high-performing team environment. Responsibilities include managing technicians, setting priorities, performance management, monitoring metrics, incident escalation, process improvement, stakeholder collaboration, and budget management. The role requires a Bachelor's degree or equivalent management experience, with preferred experience in AMHS or similar automated manufacturing systems, factory business acumen, and experience in a shift-based manufacturing environment. | — | 0 |
| Quantum Computing Measurement Engineer This role focuses on quantum computing, specifically measuring and characterizing silicon spin qubits using cryogenic systems. It involves experimental design, data analysis, and collaboration to advance quantum processor technology. | — | 0 |
| Ocotillo Technology Fabrication Shift Group Leader This role is for an Ocotillo Technology Fabrication Shift Group Leader at Intel, responsible for managing technicians in a manufacturing environment. The role involves ensuring performance, development, and employee relations, creating roadmaps to meet goals in safety, quality, availability, velocity, affordability, and training. Responsibilities include supervising product teams, assessing personnel and material levels, assigning tasks, monitoring workflow, establishing operating policies, and ensuring overall safety. The ideal candidate will have strong leadership, communication, problem-solving skills, and a proven track record of delivering results through people in a high-performing team culture. | — | 0 |
| Ocotillo Technology Fabrication Experienced Foundry Module Engineer Module Engineer role at Intel's Ocotillo Technology Fabrication facility in Phoenix, Arizona. Focuses on developing and defining manufacturable process modules for new technologies, selecting equipment, conducting experiments, driving process improvements, and transferring processes to high-volume manufacturing. Requires experience in semiconductor engineering and foundry operations. | — | 0 |
| CPU Formal Verification Engineer The role focuses on formal verification of IP and SoC microarchitectures using advanced tools and methodologies like model checking and equivalence checking. Responsibilities include developing test plans, creating abstraction models, developing formal proofs, and collaborating with design teams. Requires a Bachelor's or Master's degree with experience in formal verification and tools like Jasper. | — | 0 |
| Packaging Module Development Engineer Develops packaging materials technology for co-packaged optical semiconductor assemblies, collaborating with suppliers and internal teams to meet technology, quality, and cost targets. Requires expertise in optical materials, assembly processes, and semiconductor packaging. | — | 0 |
| CPU Design Verification Engineer Intel is seeking a CPU Design Verification Engineer for their ATOM team to ensure the functional correctness and performance of next-generation, power-efficient processors. Responsibilities include developing verification plans, creating UVM-based testbenches, performing coverage analysis, executing system-level simulations, debugging pre-silicon environments, and collaborating with architects and designers. The role requires programming skills in Python, Perl, or C++, and knowledge of computer architecture fundamentals. | — | 0 |
| Silicon Packaging Design Engineer Designs and implements physical layout and routing of silicon interposers and embedded bridges, collaborating with silicon, technology development, and hardware teams to optimize system-level design. Utilizes EDA tools for package layouts and analyzes design data to resolve checks for manufacturability. | — | 0 |
| Ocotillo Technology Fabrication Experienced Module Engineer Experienced Module Engineer for Ocotillo Technology Fabrication (OTF) at Intel in Phoenix, Arizona. This role focuses on defining roadmaps, establishing process flows, selecting materials and equipment, conducting experiments, driving process improvements, and transferring processes to high-volume manufacturing. Requires a strong background in semiconductor engineering and experience supporting manufacturing ramps and technology transfers. | — | 0 |
| Ocotillo Technology Fabrication Module Engineer Seeking an Ocotillo Technology Fabrication Module Engineer to own and manage 300mm toolsets in a high-volume manufacturing facility. Responsibilities include ensuring safety, cleanliness, process stability, and driving continuous improvement to meet yield, availability, and cycle time goals. The role involves defining roadmaps, selecting equipment, conducting experiments, developing solutions, establishing process control systems, and transferring processes to manufacturing. Experience in advanced node semiconductor foundry and supporting manufacturing ramps is required. | — | 0 |
| Physical Verification Engineer Intel Foundry Services is seeking a Senior Physical Verification Application Engineer to provide technical support to customers on layout verification and parasitic extraction for advanced CMOS processes. The role involves resolving complex physical design challenges, developing technical content, leading verification methodology improvements, and engaging with customers. Requires experience with advanced CMOS processes, EDA tools for layout verification and parasitic extraction, and scripting languages. US Citizenship and ability to obtain security clearance are required. | — | 0 |
| Design Verification Engineer Design Verification Engineer responsible for ensuring intellectual property (IP) designs meet rigorous quality standards by developing and executing verification plans, designing test benches, running simulations, and debugging pre-silicon design issues. Collaborates with cross-functional teams to verify complex architectural and microarchitectural features. | — | 0 |
| Senior Design Engineer – AI SoC Development Senior Design Engineer focused on developing logic design, RTL coding, and simulation for AI SoC development, integrating IP blocks, defining architecture, and optimizing for power, performance, and timing. The role involves collaboration with verification teams, driving silicon bring-up, and mentoring junior engineers. | — | 0 |
| Lead Senior Design Engineer – AI SoC Development Lead Senior Design Engineer for Intel's AI SoC organization, focusing on the development of logic design, RTL coding, simulation, and integration of IP blocks for AI hardware. The role involves defining architecture and microarchitecture, optimizing for power, performance, and timing, and driving silicon bring-up and validation. It requires strong engineering skills in ASIC/SoC development and leadership qualities. | — | 0 |