Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 56 active AI roles, down 14% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Intel currently has 67 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (4), GenAI Software Solutions Engineer (3), AI Software Engineer Intern (2), Graduate Talent (GenAI Software Solutions Engineer) (2), Middleware Development Engineer (2). Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (51%), agents (27%), application (9%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (20 roles), China (12 roles), Mexico (9 roles), Malaysia (8 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, fine tuning.
In the past 30 days, Intel has posted 43 new AI-related roles. That is a -45% change versus the prior 30 days (78 → 43).
| Title | Stage | AI score |
|---|---|---|
| Senior Out-of-Order CPU Architect Senior Out-of-Order CPU Architect at Intel, responsible for defining and driving end-to-end CPU architecture specifications, exploring novel architectures, and influencing cross-functional roadmaps. Requires extensive experience in high-performance CPU design and out-of-order pipeline architecture. | — | 0 |
| Senior CPU Performance Architect This role focuses on designing and specifying CPU microarchitectures, modeling their performance and power characteristics, and collaborating with cross-functional teams to ensure designs meet stringent requirements. It involves developing end-to-end specifications, evaluating tradeoffs, and debugging performance issues from RTL to silicon. | — | 0 |
| Design Engineer – AI SoC Development This role is for an RTL Design Engineer focused on developing logic design, RTL coding, and simulation for AI System-on-Chip (SoC) development. The engineer will integrate IP blocks, define architecture and microarchitecture, and optimize logic for power, performance, area, and timing. The role involves close collaboration with verification teams, physical design teams, and IP providers, and supports silicon bring-up and validation. While the products power AI applications, the core craft of the role is hardware design (RTL, SoC integration, timing closure) rather than AI/ML model development or deployment. |
| — |
| 0 |
| WLA Yield Analysis Systems Eng This role focuses on adapting, developing, deploying, and sustaining yield analysis software solutions for advanced packaging in semiconductor manufacturing. It involves driving defect data pipeline workflows, collaborating with various engineering teams, and contributing to system integration projects. The role requires a strong foundation in data analysis, programming (Python), and experience with defect and yield analysis applications, with a preference for AI/ML experience in Automated Defect Classification. | — | 0 |
| Analog and Mixed Signal Design Engineer Designs and develops analog and mixed-signal circuits for Intel's Advanced Design Foundational IP Organization, focusing on pathfinding and development of advanced logic, memory, and analog/mixed-signal circuits for Intel's process technology. | — | 0 |
| Facilities Mechanical and Controls Engineer Facilities Mechanical and Controls Engineer responsible for ensuring the reliability, performance, and safety of mechanical, HVAC, and control systems in critical environments. This role involves system design, analysis, troubleshooting, project development, and oversight of integrated facilities management partners and external vendors. Requires a Bachelor's degree in Mechanical Engineering and 5+ years of experience with mechanical and control systems. | — | 0 |
| TA/Chief of Staff for CEG This role is a Chief of Staff/Technical Assistant for Intel's Central Engineering Group (CEG), focusing on strategic initiatives, operational excellence, and stakeholder management. It requires strong business acumen, program management skills, and a deep understanding of Intel's technology and business strategies, but is not directly involved in AI/ML development. | — | 0 |
| Senior Process Engineer - Dry Etch Senior Process Engineer - Dry Etch role focused on technology development and manufacturing of semiconductor fabrication processes, specifically dry etch for advanced nodes like 18A and GAA FETs. Responsibilities include process integration, optimization, feasibility studies, and collaboration with development and manufacturing teams to support foundry customers. | — | 0 |
| Director-Analog Design & Infrastructure Design Automation Director of Analog Design & Infrastructure Design Automation to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs. | — | 0 |
| Senior CPU Verification Engineer Senior CPU Verification Engineer responsible for ensuring the functional correctness of CPU logic designs through pre-silicon verification methodologies, including developing UVM-based testbenches, running simulations, debugging issues, and collaborating with architects and designers. | — | 0 |
| Compiler Engineer Intel is seeking an experienced MSVC Compiler Engineer to work on core compiler backend components, drive performance improvements, and collaborate with hardware architecture teams for Intel platforms. Responsibilities include designing, implementing, and maintaining compiler backend optimizers and code generation, developing optimization techniques, and collaborating with hardware architects. The role also involves testing, validation, performance bottleneck analysis, staying current with compiler research, and mentoring junior engineers. | — | 0 |
| Senior Physical Design Application Engineer Senior Physical Design Application Engineer at Intel Foundry, focusing on providing technical support for Cadence tool suites, PDKs, and digital reference flows to customers. The role involves driving quality improvements in design kits, supporting successful tape-outs, and developing/optimizing digital design implementation flows for advanced CMOS processes. | — | 0 |
| IP Enablement Application Engineer Intel Foundry Services is seeking an IP Enablement Application Engineer to provide technical support to customers on IP integration challenges. This role involves working with design teams and customers throughout the IP development lifecycle, resolving issues, and providing hands-on debug. Responsibilities include customer support, cross-functional collaboration, developing integration methodologies, and creating training materials. The role requires strong problem-solving skills and experience in SOC IP Integration, RTL design, and ASIC/SoC development. | — | 0 |
| Senior Analog / Mixed Signal Application Engineer Senior Analog/Mixed Signal Application Engineer at Intel Foundry Services, providing technical support to customers on PDKs, design methodologies, and implementation flows for semiconductor manufacturing, focusing on successful customer tape-outs and quality improvements in design kits and documentation. | — | 0 |
| DFT Application Engineer DFT Application Engineer providing technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies for Aerospace, Defense, and Government (ADG) customers. The role involves customer technical support, driving quality improvements in DFT/DFM and ATPG validation methodology, and developing technical content and training. | — | 0 |
| Senior Formal Verification Engineer – AI SoC Development This role focuses on ensuring the functional correctness of complex digital designs for AI SoCs using formal methods. The engineer will own the formal verification strategy, develop environments, write properties, collaborate with design teams, and contribute to pre-silicon verification and post-silicon debug. The role also involves defining verification plans, executing them using simulation and emulation, debugging issues, and incorporating security verification activities. | — | 0 |
| Senior Photonic-Integrated-Circuit Engineer Senior Photonic-Integrated-Circuit Engineer at Intel, responsible for the end-to-end development of silicon photonic integrated circuits, from concept and design to high-volume manufacturing. This includes system-level planning, component design and optimization, simulation, layout, testing, validation, and performance debug, working cross-functionally with various teams and foundries. Requires expertise in PIC design, simulation tools (Lumerical, RSoft, Matlab, Python), and layout tools (Cadence, KLayout). | — | 0 |
| Senior Foundry Device Engineer Senior Device Engineer role at Intel, focusing on developing and customizing CMOS device technology for foundry customers. Responsibilities include collaborating with development and manufacturing teams, owning NPI, performing device optimizations, and utilizing data analysis for learning. Requires strong CMOS device physics knowledge and experience in advanced transistor architectures, preferably in a foundry environment. | — | 0 |
| GPU Physical Design Engineer Lead This role is for a GPU Physical Design Engineer Lead at Intel, focusing on ASIC design for graphics and AI SoCs. Responsibilities include floor-planning, clocking, synthesis, GDS, static timing analysis, formal verification, and EM/IR/PDN verification. The candidate will lead a small team and interact with architecture and design teams to improve IP and product quality. Requires a Bachelor's or Master's in Electrical/Computer Engineering with significant relevant experience in VLSI/ASIC design flows. | — | 0 |
| Director - Foundry Business Development This role is for a Director of Foundry Business Development at Intel, focusing on sales and customer engagement within the semiconductor industry, particularly for the AI era. The responsibilities include developing sales plans, building relationships, negotiating deals, and managing customer forecasts. While the company operates in the AI era and the role supports semiconductor manufacturing for AI, the core function is sales and business development, not direct AI/ML development. | — | 0 |
| Lead Analog SerDes Architect/Design Engineer Lead Analog SerDes Architect/Design Engineer at Intel, focusing on high-speed connectivity for data centers. Responsibilities include defining circuit architecture, leading block level development, designing mixed-signal integrated circuits, and guiding junior engineers and test plan development. | — | 0 |
| Silicon Photonics TD Process/Product Integration Engineer | — | — |
| CPU Circuit Design Engineer | — | — |
| Planning Capabilities Analyst | — | — |
| Device Engineer | — | — |