Collateral Design and Dfm Engineer

Intel Intel · Semiconductors · California, Santa Clara, United States +2

Intel is seeking a Collateral Design and DFM Lead Engineer to join their Manufacturing Development and Customer Engineering (MDCE) organization. This role focuses on advancing technology nodes from qualification to high-yield production, developing new technologies on mature node infrastructure, and enhancing Design for Manufacturability (DFM) methodologies for improved performance, yield, and ramp-up across diverse product portfolios. The engineer will lead cross-functional teams to define and enhance DFM rules, refine yield tools and flows, and predict and develop rules to avoid design marginalities.

What you'd actually do

  1. Lead cross functional teams across process integration/ device/ yield/ design/OPC/RET/DR and DTP/CAD teams to define and enhance Design for Manufacturability rules for enhanced yield /performance and faster ramp on advanced logic technologies
  2. Enhance and feed silicon learning / sighting of yield issues for design teams to update layout /DTCO methodologies, flows to capture yield issues early in the design process
  3. Work and refine yield tools/flows inside foundry and help in inline yield detection and optimization
  4. Define/Refine DFM methodologies by understanding silicon process flows and predicting and developing rules for avoiding layout and design marginalities by working with cross functional teams

Skills

Required

  • Master or Ph.D. degree in Electrical Engineering, Physics, or related field
  • Strong understanding of DTCO skills including understanding of SRAM, Standard cells, Process Integration, Yield, and Device.
  • Experience in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects
  • Experience in scribe line layout design and process monitoring structure development

Nice to have

  • Coding/Scripting knowledge
  • Ability to switch between multiple projects and ability to prioritize
  • exposure to foundry ecosystem with understanding of customer design flows and manufacturing constraints across various application domains
  • Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs, Backside power delivery
  • Understanding of Physical Design flows for Yield Analysis, DRC, and verification flows
  • Proficiency in design rule development, validation, and waiver management processes

What the JD emphasized

  • 10+ years of experience in DTCO and/or DFM within semiconductor foundry or advanced technology development environment
  • Proven track record in foundry environment developing and implementing DFM solutions for varied customer requirements across multiple market segments