Mixed Signal Design Verification Engineer

Intel Intel · Semiconductors · Bangalore, India

Mixed Signal Design Verification Engineer responsible for ensuring the quality and functionality of mixed signal components like PCIE, UCIE, and USB4/Type-C PHYs using methodologies like System Verilog, UVM, and Verilog. The role involves developing verification plans, test benches, simulation models, and conducting root cause analysis. Scripting skills in Python, Perl, or Tcl are required, along with familiarity with standard protocols and EDA tools.

What you'd actually do

  1. Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure compliance with design specifications.
  2. Develop comprehensive IP verification plans, test benches, and environments to achieve thorough coverage of mixed signal microarchitecture specifications.
  3. Define and execute simulation models to verify design performance, analyze power and timing, and identify and resolve design bugs.
  4. Conduct root cause analysis and implement corrective measures to address failing tests in the pre silicon environment.
  5. Collaborate with digital and analog architects, RTL developers, and physical design teams to refine and optimize architectural and microarchitectural features.

Skills

Required

  • Bachelor's or Master's degree in electronics and communication or electrical engineering, VLSI Engineering, or a related field.
  • 4+ years of experience with a Bachelor's degree, or 3+ years of experience with a Master's degree in ASIC or IP verification, subsystem and function coverage.
  • Proficiency in mixed signal verification and hands on in IP verification using System Verilog, UVM, and Verilog.
  • Hands-on experience with industry-standard EDA tools, such as Synopsys VCS, Cadence Xcelium, or Mentor Questa, for simulation and verification.
  • Strong scripting skills in Python, Perl, or Tcl for automation and efficiency in testbench development.
  • Familiarity with standard protocols including JTAG, IJTAG, CRI, and APB, as well as multi-clock domain mixed signal designs.
  • Expertise in constraint-random test generation, root cause analysis, and debugging of complex mixed signal designs.

Nice to have

  • Experience with low-power design techniques, including UPF and clock gating, to optimize power consumption.
  • Knowledge of Formal Property Verification tools and version control systems such as Git or Perforce.
  • Strong collaboration and communication skills with the ability to thrive in a dynamic, multi-disciplinary team environment.

What the JD emphasized

  • mixed signal components
  • IP verification
  • System Verilog
  • UVM
  • Verilog
  • EDA tools
  • Python
  • Perl
  • Tcl
  • standard protocols
  • constraint-random test generation
  • root cause analysis
  • debugging