Physical Design Engineer

Intel Intel · Semiconductors · Bangalore, India

Performs physical design implementation of custom IP and SoC designs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, static timing analysis, power/clock distribution, reliability, power/noise analysis, and verification/signoff. Optimizes design for power, frequency, and area, and participates in methodology development and flow automation.

What you'd actually do

  1. Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
  2. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  3. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
  4. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
  5. Optimizes design to improve productlevel parameters such as power, frequency, and area.

Skills

Required

  • Electrical Engineering
  • Electronics Engineering
  • Synthesis
  • place and route
  • timing analysis
  • optimization
  • IR drop analysis
  • reliability analysis
  • layout verification
  • backend sign off
  • SoC designs
  • EDA tools

Nice to have

  • automation
  • collaboration
  • architecture
  • clocking
  • logic design
  • integration
  • timing validation
  • analytical skills
  • problem-solving skills
  • innovation
  • methodologies
  • high-performance technologies
  • low-power technologies

What the JD emphasized

  • 4+ years of experience with a Bachelor's degree or 3+ years of experience with a Master's degree in Synthesis, place and route, timing analysis, and optimization, IR drop, reliability analysis, layout verification and backend sign off for SoC designs.