Job Details:
Job Description:
Mission, Team Context The HIPD SAM team is responsible for delivering end-to-end Physical Design and Analog Layout for Intel's Client, Server and ASIC Hard-IP portfolios, as well as advanced testchips for IP and SoC functional blocks. The team supports implementation from RTL/Netlist through GDSII and executes using established Physical Design methodologies and sign-off practices.
The Role and Impact The Physical Design Engineer (Grade 6) is a hands-on individual contributor responsible for block-level Physical Design execution of Hard-IPs and Testchips. The role requires consistent delivery under defined methodologies, clear ownership of assigned design blocks, and strong execution rigor while building toward broader end-to-end responsibility.
Key Responsibilities • Own block-level Physical Design from netlist handoff through GDSII under established methodologies. • Execute floorplanning, power intent setup, placement, CTS, routing, optimization, and ECO closure. • Run and debug Physical Design flows using standard tool environments. • Support physical sign-off activities including DRC/LVS and directed IR/EM analysis. • Analyze and improve QoR metrics (timing, power, area) for assigned blocks. • Use and enhance scripting and automation to improve productivity and execution quality. • Partner with Logic, STA, Analog Layout, and Methodology teams to resolve design issues. • Follow SAM-defined execution standards, checklists, and quality gates.
Qualifications:
Minimum Qualifications
- Bachelor's degree in Electrical, Electronics Engineering, or a related field.
- 3+ years of experience with a Bachelor's degree, 2+ years of experience with a Master's degree, or 0 years of experience with a PhD.
- Proficiency in Netlist-to-GDSII implementation, including floor planning, placement, clock tree synthesis, routing, and power integrity analysis.
- Hands-on experience with physical design methodologies in lower technology nodes.
- Proficiency in scripting languages such as Tcl, Perl, or Python for automation and flow optimization.
- Expertise in EDA tools and timing constraints for static timing analysis and timing closure.
Preferred Qualifications
- Mastery of VLSI circuits, design techniques, and sub-micron CMOS technologies.
- Experience in designing high-speed, low-power digital circuits and resolving timing convergence issues.
- Knowledge of hardware description languages such as Verilog or SystemVerilog.
- Inspirational leadership style and strong communication skills for collaboration in a global environment.
Your impact starts here-join Intel and be a part of transforming the world through technology innovation.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
- ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.