Pre and Post Silicon Validation Engineer

Intel Intel · Semiconductors · Bangalore, India

This role is for a Pre and Post Silicon Validation Engineer within Intel's AI Group. The primary focus is on validating the silicon behind Intel's advanced AI platforms, specifically GPUs, Cache, and PCIe technologies in complex AI SoCs. Responsibilities include defining validation strategy, executing pre- and post-silicon validation, debugging complex system-level issues, and developing validation tests and automation. The role requires strong understanding of CPU, GPU, PCIe, and memory management unit architectures, along with expertise in C/C++, Python, and Linux toolchains. While the role is within the AI Group and deals with AI hardware, the core craft is silicon validation, not AI/ML model development.

What you'd actually do

  1. Lead post-silicon validation for one of following domains in AI accelerators and SoCs: accelerators, Coherency, GPU, PCIe, Memory Management unit and debugging.
  2. Define validation strategy, coverage, and debug methodology across multiple high-speed interfaces.
  3. Mentor and provide technical guidance to junior and mid-level validation engineers.
  4. Execute pre-silicon and post-silicon validation, drive first power-on, bring-up, characterization, and production readiness activities.
  5. Debug complex, system-level issues spanning protocol, firmware, electrical, and platform layers.

Skills

Required

  • BTech /MTech in Computer Engineering, Electronics Engineering, or related field with 7+ years of relative experience.
  • Strong understanding of Memory management unit, Cache, CPU and PCIe architecture and specifications.
  • Pre/Post-silicon Validation experience to MMU, coherence, GPU, PCIe with excellent analytical and debug skills
  • Expertise in debugging memory coherency, CPU, GPU and memory specific Bugs Linux system /User mode programming
  • Knowledge on C, C++, Python, and linux tool chain
  • Knowledge in Intel/ARM based AI platform architecture and debug tools/frameworks

Nice to have

  • Good exposure on Zebu, Palladium emulation platform for validation and debugs using Lauterbach

What the JD emphasized

  • AI accelerators
  • AI SoCs
  • post-silicon validation
  • pre-silicon and post-silicon validation
  • debug complex, system-level issues