Senior Cpu Rtl Design Engineer

Intel Intel · Semiconductors · Texas, Austin, United States +1

Senior CPU RTL Design Engineer responsible for logic design, RTL coding, and simulation for CPU IP blocks. The role involves defining architecture and microarchitecture features, optimizing logic for power, performance, and area, and providing technical leadership to the design team. Experience with Timing Closure, Power Convergence, and OOO execution is required.

What you'd actually do

  1. Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs.
  2. Participates actively in the definition of architecture and microarchitecture features of the CPU being designed.
  3. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
  4. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
  5. Provide technical leadership and support to the design team leadership including proposing creative, innovative methodology and process initiatives to consistently improve efficiency and quality.

Skills

Required

  • CPU microarchitecture
  • logic design
  • RTL coding
  • Timing Closure
  • Power Convergence
  • OOO execution
  • reservation station design
  • technical leadership

Nice to have

  • x86 CPU microarchitecture
  • driving front end methodologies
  • championing the use of automation / AI tools

What the JD emphasized

  • 6+ years of experience in silicon development in CPU microarchitecture and logic design.
  • 5+ years of experience in technical leadership including delivering successful IP Projects.
  • 6+ years of experience with Timing Closure, Power Convergence; integer and/or floating point, OOO execution, reservation station design