Job Details:
Job Description:
As a Senior Physical Design Engineer, you will play a pivotal role in shaping the future of Intel's cutting-edge custom IP and System-on-Chip SoC designs for the Central Engineering Group. Your work will directly impact the development of innovative products that drive Intel's technology leadership and other Intel customer designs in the Client, Data Center, AI and Automotive products. From RTL to GDS, you will be responsible for implementing robust physical design solutions that optimize power, performance, and area while adhering to the highest industry standards. You will be a technical lead for a team to drive the SoC/Subsystem level implementation and drive convergence while meeting the PPA goals of the SOC. This is an opportunity to collaborate with world-class teams, solve complex engineering challenges, and contribute to Intel's mission of delivering transformative technology. Key Responsibilities: - Execute all stages of the physical design flow, including synthesis, floor planning, place and route, clock tree synthesis, static timing analysis, and power/clock distribution. - Perform verification and signoff tasks such as formal equivalence verification, reliability verification, static and dynamic power integrity analysis, layout verification, electrical rule checking, and structural design checking. - Analyze results to identify violations, propose solutions, and implement fixes across multiple product architecture iterations. - Optimize designs to enhance key parameters such as power, area, and frequency while ensuring high reliability and manufacturability. - Develop and refine methodologies for physical design, leveraging automation tools to improve efficiency and accuracy. - Collaborate with cross-functional teams to ensure design objectives are achieved and implement best practices for design flow and automation.
Qualifications:
Minimum Qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 15+ Years of experience in Physical Design execution. - Master's degree with 13+ Years of experience in Physical Design execution. - Deep knowledge in RTL-to-GDS workflows, including synthesis, place and route, and static timing analysis. - Expertise in optimization techniques for power, performance, and area (PPA). - Hands-on experience with industry-standard EDA tools for physical design and verification. - Comprehensive knowledge of clock tree synthesis and low-power design techniques. - Experience with competitive timing, floor planning methodologies (TFM), and multi-power domain analysis. Preferred Qualifications: - Demonstrated ability to collaborate within cross-functional teams to achieve strategic design goals. - Strong critical thinking and problem-solving skills to manage complex design challenges. - Excellent communication and organizational abilities to coordinate across disciplines. - A passion for innovation and continuous improvement in design methodologies.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
- ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.