Job Details:
Job Description:
Mission, Team Context The HIPD SAM team is responsible for delivering end-to-end Physical Design and Analog Layout for Intel's Client, Server and ASIC Hard-IP portfolios, as well as advanced testchips for IP and SoC functional blocks. The team supports implementation from RTL/Netlist through GDSII and executes using established Physical Design methodologies and sign-off practices.
The Role and Impact: As a Physical Design Timing Engineer, you will play a pivotal role in driving the success of Intel's next-generation mixed signal IPs. Your work will directly contribute to delivering high-performance, low-power designs that power innovative products and shape the future of technology. Leveraging your expertise in timing analysis and optimization, you will be integral in ensuring the efficiency, functionality, and performance of Intel's cutting-edge designs. This position offers the opportunity to collaborate with cross-functional teams, influence chip architectures, and develop methodologies that set new industry standards.
Key Responsibilities:
- Perform timing analysis and optimization to meet design specifications at the Partition and IP level levels.
- Generate and verify timing constraints, addressing timing violations across complex SoC designs.
- Conduct timing rollups, ensuring designs meet functionality, performance, and power goals.
- Develop performance and power-optimized clock networks, collaborating with clocking and backend teams.
- Define methodologies for high-quality timing models to optimize physical design team efficiency.
- Establish process, voltage, and temperature (PVT) conditions for timing analysis based on product requirements.
- Work closely with architecture, clocking design, and logic design teams to support flow development, chip integration, and clock network validation.
- Drive timing fixes, clocking balance, and power delivery through close coordination with full-chip designers.
- Ensure timing budgets are met and collaborate on timing closure reviews.
Qualifications:
Minimum Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
- 4+ years of experience with a Bachelor's degree or 3+ years of experience with a Master's degree in timing analysis and optimization for SoC designs.
- Proficiency in static timing analysis, timing budgeting, timing constraint adaptation, and clock network optimization.
- Expertise in methodologies relating to timing models, PVT conditions, and timing rollups.
Preferred Qualifications:
- Demonstrated ability to collaborate across architecture, clocking, and logic design teams to drive integration and timing validation.
- Strong analytical and problem-solving skills with an ability to innovate methodologies for efficient design processes.
- Experience with closure reviews and resolving timing violations in complex designs.
- Passion for advancing high-performance, low-power technologies and contributing to industry-leading designs.
We invite you to bring your expertise, creativity, and drive to Intel as we continue to shape the future of technology together. Apply today to be part of a team that values innovation, collaboration, and impact.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
- ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.