Silicon Photonics Foundry Pdk Design Engineer

Intel Intel · Semiconductors · New Mexico, Albuquerque, United States

Seeking a Silicon Photonics (SiP) PDK Design Engineer to join Intel's SPDM team. Responsibilities include creating and documenting pcell designs, design rules, and EDA tool flow automation. The role involves architecting, developing, and validating software solutions for Electronic-Photonic design automation, engaging with partners, and ensuring efficient cloud computing infrastructure. The candidate will lead the development of Design Environment and CI/CD pipelines for hardware and software products.

What you'd actually do

  1. Creates, modifies, and documents pcell design and related user guides.
  2. Creates, modifies, and documents design rule and other physical verification runsets.
  3. Installation and automation of EDA tool flows.
  4. Architects, designs, leads pathfinding, development, validation of software solutions in support of tools, flows, PDK design components, and methodologies used in Electronic-Photonic design automation, software products, or ecosystem enabling.
  5. Designs, develops, tests, and debugs software tools, flows, PDK design components, and methodologies used in Electronic-Photonic design automation and by teams in the design of hardware products, process design, or manufacturing.

Skills

Required

  • 2+ years of experience in Electronic Design Automation Software Development focused on Physical Verification, Layout verification, and/or run set development
  • Development of foundry rule deck (DRC and LVS) runsets.
  • Expertise in industry standard integrated circuits (IC) design CAD tools/flows such as Siemens Calibre, Cadence Virtuoso.
  • Software development/programming in high-level languages (e.g. Perl/Python/ Shell/TCL/C++).
  • Scripting and SKILL coding, Calibre SVRF/TVF and Synopsys ICValidator.
  • Analog IC or Photonic Integrated Circuit (PIC) design concepts and flows.

Nice to have

  • MS or Ph.D. with 3+ years of experience in Electronic Design Automation Software Development focused on Physical Verification, Layout verification, and runset development.
  • Developing Smart Fill decks, DRC/LVS runset development, parasitic extraction and support in EDA tools and flows such as Synopsys ICV, Siemens/Mentor Calibre, Cadence PVS/Pegasus.
  • Familiarity with Virtuoso Photonic Solutions, including hands-on experience scripting in SKILL and using Virtuoso CurvyCore concepts and implementation.
  • Experience with Synopsys OptoCompiler including the skills to design and implement photonic components and circuits using these tools.
  • Proficiency in coding and scripting for Synopsys IC Validator (ICV) to perform design rule checks (DRC) and layout versus schematic (LVS) verification.
  • Versatile in Design Tools, flows and Methods, broad expertise with Pcells, Schematic Driven Layout (SDL), Floor planning, Infrastructure and Environment set up and version control.
  • Experience in VLSI circuit, CMOS layout design and validation.
  • Experience with multiple foundry technologies.
  • Experience using Unix or Linux operating system.
  • Test case generation automatic and manual, QA and validation.
  • Expert technical problem solver with hands on execution experience with TI, TO process for complex hierarchical designs.