Soc Logic Design Engineer

Intel Intel · Semiconductors · Bangalore, India

Develops logic design, RTL coding, and simulation for SoC designs, integrating IP blocks. Participates in architecture definition, performs quality checks for power, performance, area, and timing, and ensures design integrity for physical implementation. Reviews verification plans, resolves RTL test failures, and follows secure development practices. Works with IP providers for SoC-level integration and validation, driving quality assurance for IPSoC handoff. Responsible for Xeon SoC integration in the FE domain.

What you'd actually do

  1. Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
  2. Participates in the definition of architecture and microarchitecture features of the block being designed.
  3. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
  4. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
  5. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Skills

Required

  • BSEE/CE minimum, MS preferred
  • 10 plus years' experience in IC/SoC Design and Micro Architecture
  • Experience in all phases of logic development lifecycle from high-level specification to tape-out and production
  • Expertise in X86 Server Micro Architecture Reset and Clocking Power Management DFX - Scan, JTAG, VISA, Integration etc.
  • Excellent communication and documentation skill
  • Skilled to influence in heavily matrixed environment
  • Capable to operate in ambiguity where roles may not be clearly defined or teams across multiple/functions and IP/SOC must be pulled together

What the JD emphasized

  • 10 plus years' experience in IC/SoC Design and Micro Architecture
  • Expertise in one or more of the following domains X86 Server Micro Architecture Reset and Clocking Power Management DFX - Scan, JTAG, VISA, Integration etc.