Soc Subsystem Architect - AI Platform Development

Intel Intel · Semiconductors · Bangalore, India

Intel's AI SoC organization is seeking an experienced SoC Subsystem Architect to lead the evaluation of architectural trade-offs, define and document micro-architecture for complex SoC IP blocks, and drive silicon bring-up and post-silicon validation for AI hardware. The role involves RTL design, integration, verification, timing constraints, and mentoring junior engineers.

What you'd actually do

  1. Lead evaluation of architectural trade-offs considering features, performance targets, power constraints, and system limitations.
  2. Define and document micro-architecture for complex SoC IP blocks; implement RTL in Verilog/SystemVerilog, integrate at top level, and deliver fully verified, synthesis- and timing-clean designs.
  3. Collaborate closely with verification teams to ensure comprehensive coverage and robust validation of all design aspects.
  4. Develop and maintain timing constraints for IP blocks; provide guidance and support to physical design teams for synthesis, timing closure, and formal equivalence checks.
  5. Drive silicon bring-up and post-silicon validation, including debug and performance analysis.

Skills

Required

  • RTL design and implementation for ASIC/SoC development
  • Verilog/SystemVerilog
  • SoC system integration
  • multicore CPU subsystem design
  • standard bus protocols (AXI, AHB, etc.)
  • embedded processor architectures
  • high-speed and low-power design techniques
  • EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), FPGA prototyping tools (Xilinx Vivado, Altera Quartus II)
  • clock domain crossings
  • power optimization
  • timing closure

Nice to have

  • Scripting (Python, TCL, etc.) for automation and design flow optimization
  • Mentor junior engineers

What the JD emphasized

  • 10+ years of experience in RTL design and implementation for ASIC/SoC development.