Static Timing Analysis Engineer

Intel Intel · Semiconductors · Bangalore, India

This role focuses on Static Timing Analysis (STA) for next-generation SoCs, ensuring optimal performance and efficiency. Responsibilities include performing timing analysis and optimization, generating and verifying timing constraints, resolving timing violations, conducting timing rollups, developing power-optimized clock networks, and defining methodologies for quality timing models. The role requires collaboration with various engineering teams to achieve clocking balance and power delivery optimization.

What you'd actually do

  1. Perform timing analysis and optimization to ensure design functionality and performance at the chip and block levels.
  2. Generate and verify timing constraints, addressing and resolving timing violations during SoC development.
  3. Conduct timing rollups, develop and implement power-optimized clock networks, and ensure alignment with high-performance, low-power guidelines.
  4. Define and implement methodologies to deliver quality timing models that enhance the efficiency of the physical design process.
  5. Set process, voltage, and temperature (PVT) conditions for timing analysis based on product plans and operating conditions.

Skills

Required

  • static timing analysis tools and methodologies
  • timing modeling
  • verification
  • constraint generation
  • optimization techniques
  • PVT conditions
  • SoC development
  • clocking design principles
  • timing methodologies

Nice to have

  • collaboration skills
  • high-performance computing
  • low-power design environments