AMD currently has 35 active AI-related job listings. The majority of these roles, 66%, are focused on serving infrastructure. Engineering is the dominant function, with 32 positions. Frequent technical tags include model_serving, inference_infra, and evals, suggesting a focus on the deployment and evaluation of AI models. In the last 30 days, AMD posted 37 new AI roles.
AMD currently has 62 active AI-related roles in our index. The most common open titles are: DC-GPU Performance Modeling Engineer (3), Data Center Engineer (2), Lead Packaging Automation Engineer (2), 3D IC and ADVANCED PACKAGING CAD ENGINEER , AI Framework Engineer. Most positions are in Engineering and Research.
AMD's active AI hiring is concentrated in: serving infrastructure (73%), agents (13%), application (6%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
AMD is hiring AI talent in: United States (27 roles), India (13 roles), China (7 roles), Canada (6 roles).
Job postings at AMD most frequently mention: GPU Computing, Computer Architecture, Compiler Design, Python, Performance Profiling.
In the past 30 days, AMD has posted 50 new AI-related roles. That is a -28% change versus the prior 30 days (69 → 50).
| Title | Stage | AI score |
|---|---|---|
| Software Development Engineer - Physical AI Software Development Engineer for AMD's Physical AI team, focusing on next-generation platforms for automotive and robotics. The role involves developing and integrating software for embedded Linux systems, close to hardware, with opportunities in embedded AI inference, computer vision, and robotics. | Serve | 5 |
| MTS Silicon Design Engineer This role is for an MTS Silicon Design Engineer at AMD, focusing on designing ASIC solutions for next-generation data center networking. The work involves the full development lifecycle from architecture to RTL implementation and verification, specifically enabling large-scale AI training and inference clusters. The role requires strong ASIC/SoC design experience and understanding of hardware/software trade-offs, with preferred experience in AI infrastructure silicon and AI/ML workloads. | — |
| 5 |
| Lead GPU Formal Verification Engineer Lead GPU Formal Verification Engineer at AMD in Cambridge, UK. This role focuses on driving cutting-edge formal verification techniques for next-generation graphics IP design, defining strategy, methodology, and infrastructure. The ideal candidate will have proven experience in formal verification for complex processors and leadership skills to guide the formal verification team. | — | 0 |
| Senior Virtual Software Modeling Engineer Develop Fast Platform Models that simulate software-visible behavior of AMD’s next-generation designs to enable pre-silicon development of firmware, system, driver and application software. This role involves developing high-performance C++ functional models of AMD SoCs and platforms, working closely with architecture teams, improving existing models, developing tests, and assisting customers with debugging workloads on models. | — | 0 |
| Engineering Manager – Technical Program Delivery (Embedded Systems) Engineering Manager responsible for end-to-end delivery and execution of multiple concurrent engineering projects within CXE, focusing on multi-project delivery leadership, cross-project engineering execution, and organisational coordination. | — | 0 |
| Fellow Software Development Engineer (Network Technology Group) Software engineer, architect, and technical lead for embedded firmware on AMD networking products, focusing on next-generation networking for cloud, hyperscale data centers, and AMD's AI systems. Involves hardware/software interface, C programming, system-level problem-solving, and collaboration with silicon, driver, and test teams. | — | 0 |
| MTS Silicon Design Engineer This role is for an MTS Silicon Design Engineer at AMD, focusing on architecting and delivering high-performance ASIC solutions for next-generation data center networking. The work involves the full development lifecycle from architecture to RTL implementation, verification, and validation, with a focus on solving system-level challenges for AI training and inference clusters. The role requires strong ASIC design experience and a system-level mindset, with a preference for experience in high-speed networking, data center, or AI infrastructure silicon. | — | 0 |
| HR Business Partner Manager (12 months fixed - term) This is an HR Business Partner Manager role at AMD, supporting the EMEA region. The role focuses on advancing HR initiatives, organizational development, and HR programs, acting as a strategic partner to business and HR leaders. It requires extensive experience in HR leadership across multiple European countries, strong execution skills, and the ability to influence stakeholders. While AMD is involved in AI, this specific role is not directly building or researching AI/ML models. | — | 0 |
| Python Developer in Test This role is for a Python Developer in Test at AMD, focusing on system-level validation of networking, low-latency Ethernet Adapters, and SmartNIC technology. The position involves designing, writing, and executing comprehensive, automated test cases using modern frameworks and a home-grown toolchain. The engineer will analyze results, debug issues, and collaborate with development teams to ensure products meet end-customer requirements. The role requires strong Python skills, understanding of software engineering principles, data structures, algorithms, operating systems, and multi-threaded programming, with experience in Linux and modern development tools. Familiarity with networking protocols is a plus. | — | 0 |
| Senior FPGA ASIC Design Engineer This role is for a Senior FPGA ASIC Design Engineer at AMD, focusing on the design, integration, and validation of IPs and subsystems for FPGA and ASIC platforms. The role involves technical leadership, mentoring junior engineers, and contributing to advanced projects in markets like wireless communications, aerospace, and defense. While the company mentions AI and next-generation computing, the core responsibilities are in hardware design (FPGA/ASIC) rather than AI/ML model development. | — | 0 |
| Staff Digital Design Engineer - DSP | — | — |