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Intel

Intel

Semiconductors

HQ
Santa Clara, US
Founded
1968
Size
120,000+
Website
intel.com

Currently tracking 65 active AI roles, up 115% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).

Hiring
65 / 72
Momentum (4w)
↑+268 +115%
501 opens last 4w · 233 prior 4w
Salary range · avg $253k
$122k–$414k
USD · disclosed roles only
Tracked since
Feb 3
last role yesterday
Hiring velocityscroll left for older weeks
2 new roles
Oct 6
1 new role
Dec 8
3 new roles
Jan 5
5 new roles
12
1 new role
19
2 new roles
26
6 new roles
Feb 2
6 new roles
9
8 new roles
16
18 new roles
23
22 new roles
Mar 2
38 new roles
9
45 new roles
16
29 new roles
23
37 new roles
30
54 new roles
Apr 6
113 new roles
13
110 new roles
20
151 new roles
27
166 new roles
May 4
74 new roles
11

Jobs (5)

65 AI · 728 total active
FilteredCountryJapan×
Show
Active onlyAI only (≥ 7)
Stage
AllData · 13Post-train · 6Serve · 62Agent · 13Ship · 6
Function
AllEngineering · 690Product · 25Research · 13
Country
AllUnited States · 296Malaysia · 98India · 94China · 55Mexico · 54Israel · 49Vietnam · 18Taiwan · 13Costa Rica · 12Poland · 12Canada · 11Ireland · 10Japan · 5Romania · 3Germany · 1Indonesia · 1Philippines · 1South Korea · 1
Sort
AI scoreRecentTitle
TitleStageFunctionLocationFirst seenAI score
Data Analyst (Disability Hire)
This role focuses on data analysis and developing AI/ML techniques for manufacturing processes within Intel Foundry. The primary responsibilities include developing data acquisition and analysis scripts, creating visualization dashboards, and exploring foundational AI/ML to improve pattern detection and automate analyses in manufacturing data. The role requires foundational understanding of AI/ML concepts and experience with data analysis tools and programming languages.
DataEngineeringTokyo, Japan3w ago5
Senior Program Manager
This role is for a Senior Program Manager in Intel's Advanced Packaging Technology Development Substrate and Wafer Assembly team. The focus is on developing and delivering advanced substrate packaging and wafer assembly solutions, particularly for next-generation AI devices. Responsibilities include collaborating with suppliers, driving innovation, qualifying new capacity, optimizing processes, managing schedules, and ensuring adherence to quality standards. The role requires strong technical expertise in semiconductor manufacturing processes and supplier management.
—
Engineering
Tokyo, Japan
5d ago
0
Memory Research Scientist
Memory Research Scientist at Intel in Tokyo, Japan, focusing on AI/HPC, compute architecture, memory technology, and advanced system architecture. The role involves leading technical engagement for the ZAM NEDO program, coordinating with partners and US-based teams, and driving applied research for Japanese government/commercial initiatives. Requires deep experience in semiconductors, full development lifecycle, and strong technical coordination between US and Japanese teams.
—ResearchTokyo, Japan4w ago0
Sr. Substrates Development and Ramp Engineer
Senior engineer focused on supply chain and logistics strategy, process and quality improvements, cost control, production yield optimization, and supplier management within Intel's semiconductor manufacturing environment. Requires deep knowledge of substrate manufacturing, raw materials, packaging technologies, and quality systems.
—EngineeringTokyo, Japan8w ago0
Advanced Packaging Materials Supply Chain Engineer
Supply Chain Engineer at Intel responsible for developing and executing supply chain strategies, ensuring supplier process and product readiness, and managing supplier relationships to meet cost, quality, availability, technology, and environmental goals within the semiconductor industry.
—EngineeringTokyo, Japan8w ago0