Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 65 active AI roles, up 115% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
| Title | Stage | AI score |
|---|---|---|
| Thermal Engineering Intern Seeking a Thermal Intern to support thermal engineers with lab testing, data collection, and documentation. Responsibilities include assisting with thermal modeling setup, analyzing airflow and temperature data, and documenting results. The role involves working within a cross-functional Architecture/Engineering team focused on Co-Engineering Custom Design Systems with strategic customers and driving new platform-level innovations. | — | 0 |
| Atom CPU Layout Design Engineer Intel is hiring an Atom CPU Layout Design Engineer in Guadalajara, Mexico. The role involves the physical implementation of memory compilers, custom IP blocks, and layout partitions for future-generation Intel Atom microprocessors. Responsibilities include ensuring best-in-class layout methodologies, performing complex physical design assignments, interpreting schematics, contributing to the full design flow, and partnering with SoC teams. The ideal candidate will have 2+ years of layout design experience and strong analytical skills. A Master's degree and experience with VLSI/CMOS logic circuit design are preferred. | — |
| 0 |
| Soc Functional Validation Engineering Intern Internship role supporting SoC (System on Chip) development activities, focusing on learning about functionality, performance, and quality validation of integrated SoCs. Responsibilities include assisting in developing and executing Pre-Silicon validation plans and supporting Post-Silicon validation activities under supervision. | — | 0 |
| CPU Pre-Silicon Verification Engineer Senior CPU Pre-Silicon Verification Engineer responsible for ensuring the functional correctness and robustness of CPU logic designs through pre-silicon verification methodologies. This involves developing and maintaining verification environments, test plans, coverage models, and debugging RTL and testbench failures. The role requires close collaboration with microarchitecture, design, and post-silicon teams to deliver high-performance, power-efficient, and reliable CPU IP. | — | 0 |