Meta currently has 129 active AI-related job listings. The hiring is most concentrated in the application stage, representing 22% of the roles, followed closely by agents at 20% and pre-training at 16%. Research is the dominant function, with 63 roles, followed by Engineering with 52. The majority of these positions are located in the United States. Frequent tech tags include agent_orchestration, frontier_research, and multimodal. Over the last 30 days, Meta posted 18 new AI roles, a 31% decrease compared to the previous 30-day period.
Currently tracking 121 active AI roles, up 55% versus the prior 4 weeks. Primary focus: Ship · Research.
Meta currently has 136 active AI-related roles in our index. The most common open titles are: Business Support Engineer (5), AI Research Scientist, Robotics (3), Business Engineer, Business AI (3), Software Engineer, Systems ML (3), AI Research Scientist, VLM (vision language models) (2). Most positions are in Engineering and Research.
Meta's active AI hiring is concentrated in: agents (23%), application (20%), serving infrastructure (16%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Meta is hiring AI talent in: United States (108 roles), United Kingdom (9 roles), France (7 roles), Singapore (6 roles).
Job postings at Meta most frequently mention: Machine Learning, Large Language Models (LLMs), Robotics, Agentic Systems, Generative AI.
In the past 30 days, Meta has posted 67 new AI-related roles. That is a +103% change versus the prior 30 days (33 → 67).
| Title | Stage | AI score |
|---|---|---|
| ASIC DV Engineer, Simulation Acceleration and Hybrid Verification ASIC DV Engineer with background in Simulation Acceleration using Emulation and Hybrid Platforms for data center applications. Responsibilities include proposing and implementing verification methodologies, developing test plans, debugging functional failures, and building reusable verification environments. Requires experience with Verilog, SystemVerilog, UVM, C/C++, Python, and hardware platforms like Zebu, Palladium, Veloce. | — | 0 |
| ASIC Engineer, Infrastructure Specialist Meta is seeking an ASIC Engineer, Firmware Specialist in Bangalore, India, to architect, design, build, and test embedded firmware systems for future ASIC platforms. The role involves defining architecture, implementing designs, and developing secure bootloaders, low-level device drivers, and RTOS-based platform firmware for data center chips. Responsibilities include technical leadership, firmware analysis, development, debugging, and supporting hardware development phases from silicon definition to chip bring-up. The ideal candidate will have 6+ years of experience in embedded system development with C, experience in BootROM/bootloaders, complex SoC firmware, and RTOS environments, along with expertise in areas like SoC block understanding or board bring-up. |
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| 0 |
| ASIC Engineer, Design Verification Meta is seeking an experienced ASIC Design Verification Engineer to join their Infrastructure organization in Bangalore, India. The role involves developing innovative ASIC solutions for data center applications, focusing on verification closure of IP and SoC modules. Responsibilities include defining verification plans, developing test benches using UVM, debugging failures, and collaborating with cross-functional teams. The ideal candidate will have 6+ years of experience in ASIC design verification, proficiency in Verilog, SystemVerilog, C/C++, UVM, and EDA tools, and a track record of first-pass silicon success. Experience with ARM/RISC-V based systems and data center applications (including AI/ML) is also mentioned. | — | 0 |
| ASIC Engineer, Design Verification ASIC Design Verification Engineer responsible for verification closure of design modules or sub-systems for data center applications and wearables, using simulation, Formal, and Emulation. Requires expertise in SystemVerilog/UVM, test bench development, and collaboration with cross-functional teams. | — | 0 |
| ASIC Engineer, Design Verification Seeking an ASIC Design Verification Engineer for Meta's Infrastructure organization in Bangalore, India. The role involves verifying IP and SoC for data center applications, including AI/ML designs. Responsibilities include defining verification plans, developing testbenches using UVM, driving verification closure through simulation, formal methods, and emulation, and collaborating with cross-functional teams. Requires 8+ years of experience in SystemVerilog/UVM, with experience in AI/ML design verification and high-speed interfaces being a plus. | — | 0 |