Advanced Packaging Technologist & Lead

Cerebras · Semiconductors · Headquarters +1 · Systems

The role is for an Advanced Packaging Technologist & Lead responsible for developing and deploying next-generation semiconductor packaging technologies for AI chips. This includes designing 2.5D/3D stacking, heterogeneous integration, and optimizing bonding approaches like Chip-on-Wafer and Wafer-to-Wafer. The role also involves material selection, process technology development, and ensuring reliability for high-performance compute and AI applications.

What you'd actually do

  1. Design and implement advanced semiconductor packaging technologies, including 2.5D/3D stacking, heterogeneous integration, high-bandwidth interconnects, and advanced power-delivery architectures.
  2. Lead R&D in Chip-on-Wafer (CoW) and Wafer-to-Wafer (W2W) bonding approaches for high-density integration.
  3. Develop and optimize solutions using silicon interposers, Through-Silicon Vias (TSVs), and multi‑layer RDL packaging to enable ultra‑high‑bandwidth and low‑latency connections.
  4. Engineer advanced packaging structures using low‑CTE substrates, FLEX interconnects, and organic or ceramic substrate technologies.
  5. Align internal architects and external partners to deliver manufacturable designs and steer our strategic technology direction.

Skills

Required

  • BS EE, MS EE or equivalent engineering discipline
  • 10+ years of experience in advanced packaging

Nice to have

  • working knowledge of simulation tools (i.e. Ansys, Cadence, Abaqus)

What the JD emphasized

  • 2.5D/3D stacking
  • heterogeneous integration
  • Chip-on-Wafer (CoW)
  • Wafer-to-Wafer (W2W)
  • silicon interposers
  • Through-Silicon Vias (TSVs)
  • multi‑layer RDL packaging
  • low‑CTE substrates
  • FLEX interconnects
  • organic or ceramic substrate technologies
  • deliver manufacturable designs
  • steer our strategic technology direction
  • advanced buildup substrates
  • flip-chip bonding
  • solder balls
  • copper pillars
  • substrate embedding
  • advanced dicing methodologies
  • Select materials
  • enable high performance, manufacturability, and reliability
  • package-level and board-level qualification
  • solder reliability
  • ultra-thin die handling and processing
  • backside metallization
  • RDL process development
  • failure analysis
  • pivot the team toward a solution