Advanced Technology: R&d Engineer - Ai/ml, Hpc

Cerebras Cerebras · Semiconductors · Headquarters +3 · Advanced Technology

Research Engineer role focused on designing and implementing AI/ML workloads on Cerebras' wafer-scale hardware, optimizing performance, and contributing to future hardware/software roadmaps. Involves algorithm-hardware co-design, performance modeling, and publishing research.

What you'd actually do

  1. Design and implement challenging scientific computing and AI workloads on Cerebras’ Wafer-Scale Engine, targeting performance results that advance the state of the art.
  2. Lead algorithm–hardware co-design efforts with internal R&D teams and external research partners, turning architectural capabilities into measurable application-level advantages.
  3. Build analytical performance models that quantify bottlenecks, guide optimization, and inform future chip and compiler design decisions.
  4. Contribute to Cerebras’ multi-year technology roadmap by identifying high-impact workloads, proposing architectural experiments, and validating them on silicon.
  5. Publish findings and present at top-tier conferences and journals; represent Cerebras in the broader HPC and AI research communities.

Skills

Required

  • Proficiency in C and Python
  • Deep experience in at least one of the following: computer architecture and accelerator design; parallel, distributed, or high-performance computing; numerical methods and scientific simulation; AI/ML theory and model design at a mathematical level.
  • Strong ability to analytically model and optimize the performance of complex systems and algorithms.
  • Excellent communication and interpersonal skills

Nice to have

  • Exceptional candidates without a graduate degree who demonstrate equivalent depth through published research, significant open-source contributions, or a strong industry track record are encouraged to apply.

What the JD emphasized

  • PhD in Computer Science, Engineering, Applied Mathematics, Physics, or a related quantitative field preferred
  • Track record of published research or patents in relevant venues
  • deep understanding of model architecture, optimization methods, and their statistical underpinnings

Other signals

  • design and implement workloads that establish new performance benchmarks on wafer-scale hardware
  • algorithm design, compiler co-optimization, and hardware architecture
  • publish findings and present at top-tier conferences and journals