Job Details:
Job Description:
You will be joining an analog/mixed-signal PLL team involved in design and development on cutting-edge Intel and external foundry process development nodes. Your responsibilities will include but not be limited to: Experience in LC VCO/DCO design. Good exposure to performance parameters of VCO as well as complete PLL architecture. Exposure to inductor custom design. Involvement in multi-dimensional 3D solver tools for inductor characterization. The candidate should have experience in Analog and Mixed Signal Design with focus on PLLs and clocking circuits. Strong fundamentals of CMOS design, passive RC circuits, switched cap circuits are a must for this role. The various task involves, circuit design, validation, mixed signal validation, and reliability validation. Exposure to PLL designs (either Charge-Pump based or ADPLLs or both, Fractional-N PLLs, spread-spectrum PLLs, etc.) High speed digital circuit design and analysis with timing and flow closure. Digitally assisted analog circuit and techniques. The candidate will be responsible for the High speed, low power, and reliable analog and digital circuits for various areas of PLL. Good knowledge of control systems, band gaps, bias, op-amps, LDOs, feedback and compensation techniques.
Qualifications:
Candidate should possess at least a Bachelor / Master of Science degree in Electrical Engineering or equivalent. Strong academic background required in CMOS semiconductor device physics and silicon processing. Relevant coursework in CMOS digital, analog, and I/O circuit design Knowledge of transistor-level circuit simulation tools such as SPICE The following preferred qualifications would be an added advantage: 5-8 years of experience in Circuit Design and/or 1-2 years experience in LC Oscillators Inductor Design Familiarity with CMOS transistor and semiconductor device layout methods. Experience using custom design environments such as Cadence design automation tools (ADS, Analog Artist, or Virtuoso) Knowledge of DRC, LVS, and post-layout extraction tools.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
- ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.