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**The Role : **The I/O Pad Ring Team is looking for a candidate to perform I/O pad ring physical verification duties and methodology improvements on multiple exciting AMD products being created today. I/O Pad Ring refers to the input/output interfaces that are loosely found in a ring around the chip. Interfaces like PLL (phase lock loop), DDR, GDDR, USB, HDMI, PCIE, GPIO all reside in the IO Pad Ring. SOC level verification takes many days now. The IO Pad Ring function takes a subset of analog IPs to pre-verify them in order to pre-fetch any issues prior to final integration. This team is essential to the success of AMD as a cutting edge company. You will be working on some of the most exciting projects the industry has to offer. CPU/ GPU / APU and semi-custom AMD's products featured in Sony Playstation and Microsoft Xbox, to name a few. It is a very exciting environment and you will be working with the very best in our technology.
**The Person : **The candidate will excel in problem solving/debug skills and be able to see through the latter stages of a product delivery. Strong communication skills will also be required for this role.
Key Responsibilities :
Day to day responsibilities include, assembly of macros/IPs/RDL into an I/O pad ring database, and then running various verification tools on that assembled database to determine integration issues. If issues are discovered, communication with various IP owners may be required to facilitate issue resolution. Some of these include Design Rule Check, Layout VS Schematics, Electronic Rule Check and Latch up/Electrical Static Discharge.
- Construction of product I/O pad rings using established flows and scripts. Generated views include: Verilog, Def, Spice, and GDSII.
- Physical verification on designs that contain up to 200M devices including: LVS, DRC, ERC and PERC.
- Delivery of all needed waivers(Electronic Rule Check /Design Rule Check /EDRC/PERC) and documentation to SoC teams
- Facilitate ESD and design reviews for 3rd party IPs and I/O ring
- Tracking of IP versions, visual inspections and in-context XOR verifications.
Preferred Experience:
- Strong understanding of physical verification checks (Layout VS Schematic /Design Rule Check /Electronic Rule Check/PERC), and ability to debug and resolve issues.
- Knowledge of chip level integration and Electrical Static Discharge /LUP concepts.
- Must have ability to communicate with various teams to articulate issues, requirements as they pertain to layout in order to facilitate solutions
- Physical verification experience using Mentor Calibre (Laoyt VS Schematic, Design Rule Check, PERC), and Synopsys tools (ICC/ICC2/ICV).
- Experience doing physical verification for tile of chip physical design would be an asset.
- Perl programming, TCL, SVRF, TVF programming not required, but would be advantages
- IP layout design experience and exposure to Cadence is a plus.
- Must be able to work independently and as part of a team
EDUCATION:
- Electrical/Computer/Biomedical/Mechanical Engineering Degree and/or Electronics related Diploma
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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
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This posting is for an existing vacancy.