Asic Design Efficiency Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +2

NVIDIA is seeking methodology engineers to design hardware accelerators and processors for their next-generation platforms, impacting product lines from consumer graphics to self-driving cars and AI. The role involves developing innovative HW/GPU/system designs for performance and efficiency, creating methodology and infrastructure for PPA improvements, and delivering verified RTL. Requires a Bachelors in EE/CE or equivalent, 2+ years of experience, proficiency in SystemVerilog, and understanding of logic design/computer architecture.

What you'd actually do

  1. Develop innovative HW, GPU and system designs to extend the state of the art performance and efficiency.
  2. Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
  3. Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets.
  4. Collaborate with architects, designers, verification and VLSI teams to craft the industries' top performing GPUs.

Skills

Required

  • SystemVerilog
  • logic design
  • computer architecture

Nice to have

  • Python
  • Perl
  • pipeline processor design
  • deep learning accelerator design/architecture
  • performance verification
  • low power design
  • physical design
  • VLSI design

What the JD emphasized

  • Bachelors Degree in EE or CE or equivalent experience.
  • 2+ years of experience.
  • Proficiency in SystemVerilog or similar HDL.
  • solid understanding of logic design and computer architecture.
  • Strong interpersonal skills are required