Asic Design Engineer - Circuits

NVIDIA NVIDIA · Semiconductors · Bangalore, India

NVIDIA is seeking an ASIC Design Engineer to join their Circuit Solutions Group. The role involves defining system-level architecture, micro-architecture, and specifications for mixed-signal chips, focusing on power delivery and power management solutions for next-generation GPUs. Responsibilities include RTL development, behavioral modeling, and collaboration with cross-functional teams throughout the ASIC design flow, from front-end to tape-out.

What you'd actually do

  1. Collaborate with cross-functional teams to define system-level architecture of mixed-signal chips for power delivery and power management solutions.
  2. Define micro-architecture and specifications of digital IP blocks to improve the power and performance of NVIDIA’s next generation GPUs
  3. Partner with RTL and Design Verification engineers to ensure delivery meets performance and quality expectations.
  4. Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/DFT/LEC/STA)
  5. Partner and work with back-end team until chip tape-out.

Skills

Required

  • B.S. or MS degree in Electrical Engineering (or equivalent experience)
  • 1+ years of proven experience and a background in logic design, Verilog and/or System-Verilog with a deep understanding of physical design and VLSI
  • Experience with RTL development, Custom Digital Design, and Behavioral Circuit Modeling for mixed-signal blocks.
  • Well-versed with Verilog/SystemVerilog
  • Strong familiarity and experience with all stages of ASIC design flow including front end design and verification, DFT, and timing analysis
  • Strong team player with outstanding interpersonal skills.

Nice to have

  • Strong knowledge or work experience in Mixed signal and custom designed IPs solutions.
  • Experience with industry standard communication standards such as JTAG, I2C, SPMI, etc.
  • Familiarity with power management IPs.
  • Understanding of firmware and embedded controllers.