Asic Design Engineer, Clocks

NVIDIA NVIDIA · Semiconductors · Shanghai, China

NVIDIA is seeking a Senior ASIC Design Engineer for their GPU clocks group. The role involves designing, architecting, and validating high-frequency, low-power clocking RTL for GPUs, collaborating with various design and verification teams, and improving design flows using scripting languages. Experience with RTL design, logic synthesis, and silicon issues is required.

What you'd actually do

  1. collaborate with other architects, ASIC designers and verification engineers to design high frequency and low power clocks
  2. engage with multiple teams and design the GPU clocks to satisfy all the architectural constraints
  3. run and enhance some in-house flow to guarantee the good quality of clocks RTL and netlist, drive the issues to close
  4. deliver clock information to SOC verification team, timing and DFT teams
  5. use Perl/Python to improve the productivity of the above teams
  6. Collaborate with software and silicon solution team to debug GPU clock silicon bugs in our new products

Skills

Required

  • RTL design (Verilog)
  • verification
  • logic synthesis
  • Perl
  • Python
  • scripting languages

Nice to have

  • sub-micron silicon issues like noise, cross-talk, and OCV effects
  • backend flows and requirements
  • DFT knowledge
  • implementing on-chip clocking networks