Asic Design Engineer, Cloud-scale Machine Learning Acceleration Team - Annapurna Labs

Amazon Amazon · Big Tech · Cupertino, CA · Software Development

ASIC Design Engineer for AWS's custom machine learning acceleration hardware (Inferentia). Focus on RTL design, microarchitecture, and optimization for performance, power, and area in data center servers.

What you'd actually do

  1. Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets
  2. Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements
  3. Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints
  4. Execute lint and clock domain crossing quality checks to ensure design integrity
  5. Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts

Skills

Required

  • Bachelor's degree in Electrical Engineering or a related field
  • Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
  • Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
  • SystemVerilog
  • ASIC design
  • analytical and problem-solving skills

Nice to have

  • Master's degree in Electrical or Communications Engineering or a related field
  • formal verification techniques including abstraction and end-to-end checking
  • ARM and various DSP ISAs
  • current and upcoming RF standards in cellular (4G/5G NR), WiMAX, 802.11ad, microwave backhaul, or related broadband wireless standards
  • industry standard tools and scripting languages (Python or Perl) for automation
  • high-performance and power-efficient designs