Asic Design Engineer, Cloud-scale Machine Learning Acceleration Team - Annapurna Labs

What you'd actually do

1. Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets
2. Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements
3. Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints
4. Execute lint and clock domain crossing quality checks to ensure design integrity
5. Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts

Skills