Asic Design Engineer - Hardware

NVIDIA NVIDIA · Semiconductors · Austin, TX

This role is for an ASIC Design Engineer focused on improving methodologies and delivering system-level IP for performance measurement on GPUs and SOCs. Responsibilities include RTL design, verification, automation, and working with cross-functional teams. Requires BS/equivalent in EE/CE, 2+ years of experience in RTL design, verification, and scripting languages.

What you'd actually do

  1. Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs
  2. Define, develop, and automate flows and methodologies to efficiently build, deliver, and support a system-level IP
  3. Deliver IP and support projects by applying the performance monitoring system
  4. Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)
  5. Design and implement RTL features (microarchitecture and RTL)

Skills

Required

  • BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree
  • 2+ years of relevant industry experience
  • Perl/Python or other industry-standard scripting languages
  • RTL design (Verilog)
  • verification (SystemVerilog)
  • System-On-Chip design/implementation flow
  • design automation
  • SOC architecture
  • CDC
  • multiple-power domains
  • performance analysis
  • latency
  • data flow
  • debugging
  • analytical skills
  • design and verification tools (dc_shell, VCS, Debussy, GDB)

Nice to have

  • advanced degrees (MS, PhD)
  • object-oriented programming
  • system level IP (Clocks/DFT/Resets)
  • developing methodologies used by others
  • silicon debug
  • physical design

What the JD emphasized

  • BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree required
  • 2+ years of relevant industry experience
  • strong coding skills in Perl/Python or other industry-standard scripting languages
  • Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chip design/implementation flow, and design automation
  • Good understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow
  • Excellent debugging and analytical skills
  • Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)