Asic Design Engineer - New College Grad 2026

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking an ASIC Design Engineer for their Memory Subsystem Team, focusing on micro-architecture, RTL design, synthesis, and timing analysis for sophisticated SOC Interconnects. The role involves collaboration with various engineering teams and requires proficiency in Verilog/VHDL and scripting languages, with exposure to high-speed interconnects and industry specifications.

What you'd actually do

  1. As a member of our Memory Subsystem Design team, you will collaborate with architects/design verification/formal verification/physical design team to deliver a world-class solution.
  2. In this position, you will have the opportunity to be responsible for the micro-architecture and design including RTL design, synthesis and timing analysis using innovative CAD tools and using the latest process technologies.

Skills

Required

  • BS or MS in Electrical Engineering or Computer Engineer or related degree
  • Verilog or VHDL
  • PERL

Nice to have

  • high-speed coherent interconnects
  • protocol bridges
  • hardware-managed coherency
  • system level caches
  • multiple clock domains
  • asynchronous interfaces
  • CHI/CXL/PCI-E