Asic Design Engineer - New College Grad 2026

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

ASIC Design Engineer role focused on CPU on-chip interconnect network, coherency, and last-level caches. Responsibilities include micro-architectural definition, RTL coding, logic debug, synthesis, timing closure, and supporting verification and implementation. Requires experience in processor or semiconductor designs, Verilog, ASIC design flow, and computer architecture.

What you'd actually do

  1. As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip.
  2. Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation.
  3. Collaborate with our verification team to verify the correctness of your unit.
  4. Work with implementation to achieve your timing, area, performance and power goals.
  5. Assist with timing closure of super units.

Skills

Required

  • BS or MS Degree in Electrical Engineering, Computer Engineering or Computer Science (or equivalent experience)
  • Verilog
  • ASIC design flow
  • RTL design
  • verification
  • logic synthesis
  • prototyping
  • DFT
  • timing analysis
  • floor-planning
  • ECO
  • bring-up & lab debug
  • computer architecture
  • cache coherency
  • high speed interconnects

Nice to have

  • processor or other related high performance semiconductor designs
  • mentoring junior engineers and interns

What the JD emphasized

  • Verilog expertise required
  • deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
  • strong background in computer architecture