Asic Design Verification Engineer

AMD AMD · Semiconductors · Austin, TX · Engineering

AMD is seeking an ASIC Design Verification Engineer to join their MSIP UMC team. The role involves all aspects of IP verification, including architecture, test plans, environment development, and closure. The engineer will work on leading-edge DDR technologies for data center and machine learning workloads, contributing to the development of client, server, embedded, graphics, and semi-custom chips. Responsibilities include collaborating with architects, taking ownership of features, developing verification environments using System Verilog/UVM/SystemC, debugging regressions, and deploying verification methodologies.

What you'd actually do

  1. Collaborate with IP architects to come up with verification architecture, verification methodology, improvements, and development plans
  2. Taking on some key technical leadership responsibilities to help current DV leads and DV Architects
  3. Participate in verification of complex IP blocks and take end-to-end ownership of key features for all projects
  4. Work on test plans, verification environment development, regression, and coverage closure
  5. Develop modifying and maintaining VIP, libraries, verification environments, testcases (random and directed) using System Verilog/UVM/SystemC

Skills

Required

  • System Verilog
  • UVM
  • OOP
  • Linux
  • Windows

Nice to have

  • ASIC verification experience
  • Strong understanding of digital design and computer architecture
  • Strong understanding and experience in block-level constrained random verification
  • C/C++
  • ASIC design knowledge
  • debug System Verilog RTL code using simulation tools
  • formal verification