Asic Design Verification Engineer - New College Grad 2026

NVIDIA NVIDIA · Semiconductors · Austin, TX

Entry-level ASIC Design Verification Engineer role focused on verifying system-level IP for NVIDIA's SOC group. Responsibilities include designing and maintaining verification environments, developing test plans, creating UVM components, and collaborating with cross-functional teams to ensure high-quality design and robust verification.

What you'd actually do

  1. Design and maintain the unit level/sub-system Verification environment.
  2. Understand the architecture specifications, develop and carry out the test plan to verify the design.
  3. Create the UVM components, sequences, tests and scoreboards.
  4. Sign off on the verification efforts with very high quality code and functional coverage.
  5. Launch regressions, resolve the issues, and make forward progress towards achieving the DV milestone targets

Skills

Required

  • System Verilog
  • UVM
  • OOPS based programming
  • Python
  • RTL design (Verilog)
  • computer architecture fundamentals
  • VCS
  • Verdi

Nice to have

  • scripting languages

What the JD emphasized

  • real passion for verification methodologies and implementation