Asic Engineer

Meta Meta · Big Tech · Austin, TX

ASIC Engineer role focused on micro-architecture, RTL development, and verification for IPs, with a focus on PPA (Power, Performance, Area) optimization. Requires a Bachelor's degree and experience in Computer Architecture, Logic Design, and RTL development using Verilog, System Verilog, or HLS.

What you'd actually do

  1. Participate in Micro-architecture, Design, and Verification reviews and provide feedback.
  2. Design and develop RTL or HLS code for some of the Ips.
  3. Analyze designs and enhance PPA (Power, Performance, Area).
  4. Support and develop Verification Infrastructure, analyze and improve Verification Coverage, Support Simulation accelerators and post-Silicon validation.
  5. Ensure that the designs are CDC and Lint clean.

Skills

Required

  • Computer Architecture
  • Logic Design fundamentals
  • RTL development using Verilog, System Verilog or HLS
  • Micro-architecture development
  • Lint
  • CDC
  • Synthesis
  • Power Optimization
  • Timing Closure
  • Formal Verification Methodology
  • TCL, Python, Perl, or Shell-scripting

Nice to have

  • HLS