Asic Engineer, Annapurna Labs

Amazon Amazon · Big Tech · Austin, TX · Hardware Development

Amazon Web Services (AWS) is seeking an ASIC Design Engineer for its Annapurna Labs team. This role focuses on the design and optimization of custom System on Chip (SoC) hardware for AWS's machine learning servers, specifically mentioning AWS Inferentia for machine learning inference. The engineer will be responsible for RTL design, microarchitecture, synthesis, and ensuring design integrity through quality checks. Collaboration with cross-functional teams is a key aspect of the role.

What you'd actually do

  1. Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets
  2. Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements
  3. Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints
  4. Execute lint and clock domain crossing quality checks to ensure design integrity
  5. Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts

Skills

Required

  • Bachelor's degree in Electrical Engineering or a related field
  • Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
  • Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
  • strong background in ASIC design
  • proficiency in SystemVerilog
  • excellent analytical and problem-solving skills

Nice to have

  • Master's degree or Ph.D. degree in Electrical Engineering or related field
  • Experience with formal verification techniques including abstraction and end-to-end checking
  • Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards
  • Experience with industry standard tools and scripting languages (Python or Perl) for automation
  • Experience with ARM and various DSP ISAs
  • familiarity with key components such as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level architectures

What the JD emphasized

  • high-performance
  • area and power-efficient
  • design quality
  • right trade-offs
  • high-performance
  • power-efficient designs
  • strong drive to innovate
  • explore new solutions