Asic Engineer, Design Verification

Meta Meta · Big Tech · Sunnyvale, CA

ASIC Design Verification Engineer responsible for developing functional tests, building verification test benches, and debugging functional failures for ASIC IPs and SoCs. Requires experience with Verilog, System Verilog/UVM, EDA tools, and scripting.

What you'd actually do

  1. Develop functional tests based on verification test plan.
  2. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
  3. Define and implement ASIC verification plans, build verifications test benches to block IP/subsystem/ SoC level verification and develop functional tests.
  4. Debug, rootcause and resolve functional failures in the design, partnering with the Design team.
  5. Collaborate with crossfunctional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality.

Skills

Required

  • Verilog
  • System Verilog/UVM methodology based verification
  • Block/IP/sub-system and/or SoC level verification based on System Verilog UVM based methodologies
  • EDA tools and scripting (Python, Shell)
  • Implementing Design Verification infrastructure (Testbench, Functional coverage, Regression setup)
  • Developing and executing verification test plans, random stimulus, coverage, and assertions
  • Debugging and root cause failures and tracking verification completion using metrics
  • Executing a full verification cycle

Nice to have

  • CPU or GPU or HW Accelerator verification