Asic Engineer, Design Verification

Meta Meta · Big Tech · Austin, TX

ASIC Engineer, Design Verification role focused on developing functional tests, driving verification to closure, defining and implementing IP/SoC verification plans, and debugging design failures. Requires experience with Verilog, System Verilog/UVM, C/C++, EDA tools, scripting, and industry standard bus protocols.

What you'd actually do

  1. Develop functional tests based on verification test plan.
  2. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
  3. Define and implement IP/SoC verification plans, build verifications test benches to block IP/subsystem/SoC level verification and develop functional tests based
  4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
  5. Collaborate with cross-functional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality.

Skills

Required

  • Verilog
  • System Verilog/UVM methodology
  • C/C++ based verification
  • Block/IP/sub-system or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • EDA tools and scripting (Python, TCL, Perl, Shell)
  • Implementing Design Verification infrastructure (Testbench, RAL based register verification, Functional coverage, or Regression setup)
  • Industry standard Bus Protocols, such as AMBA AXI, AHB, or APB