Asic Floorplan Design Engineer - New College Grad 2026

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is looking for a New College Graduate ASIC Floorplan Design Engineer to design and implement leading SoC's and GPU's. The role involves developing and optimizing floorplans, driving area reviews, solving timing and routing issues, and building tools to improve chip area and execution speed. Requires a Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering, with a background in VLSI/Computer Architecture, Verilog/System Verilog, CAD/physical design methodologies, and programming experience in Python, Perl, and C/C++.

What you'd actually do

  1. Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
  2. Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities
  3. Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
  4. You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

Skills

Required

  • Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience
  • VLSI and/or Computer Architecture background
  • Verilog, System Verilog or similar HVL
  • CAD and physical design methodologies
  • chip floorplan
  • power/clock distribution
  • packaging
  • P&R
  • timing closure
  • Python
  • Perl
  • C/C++

Nice to have

  • Experience in driving development of large scale ASIC floorplan

What the JD emphasized

  • Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
  • A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
  • Experience in Verilog, System Verilog or similar HVL
  • Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
  • Python, Perl and C/C++ programming language experience