Asic/fpga Design Engineer

Intel Intel · Semiconductors · Penang, Malaysia

Intel is seeking an experienced RTL/Logic Design Engineer to develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions. The role involves functional simulation, verification, debugging, and collaboration with cross-functional teams to ensure design quality and meet specifications. Experience with packet-based protocols and agentic AI is considered an advantage.

What you'd actually do

  1. Develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions and perform functional simulation and verification to ensure the designs meet functional and performance specifications.
  2. Debug and resolve design and simulation issues, collaborate closely with architects, verification engineers, and system teams to clarify requirements, and support design integration, bring-up, and issue resolution.
  3. Ensure high design quality by following coding standards and maintaining proper technical documentation.

Skills

Required

  • 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or System Verilog RTL coding.

Nice to have

  • Packet Based Protocols such as PCIe, USB, SPI, I2C
  • agentic AI
  • logic design and writing RTL in Verilog or System Verilog
  • internal and 3rd-party logic design tools
  • analytical ability, problem solving and communication skills
  • Gate-level understanding of RTL and synthesis
  • lab equipment such as logic analyzers, scopes, protocol analyzers
  • communication and teamwork still
  • work independently and at various levels of abstraction
  • lead a team of designer
  • FPGA design and debug with FPGA tools like Quartus/Vivado
  • embedded SW which using NIOS or ARM processor