Asic/fpga Verification Engineer - (associate, Experienced, or Lead) - Socal

Boeing Boeing · Aerospace · El Segundo, CA +1

Boeing is seeking ASIC/FPGA Verification Engineers (Associate, Experienced, or Lead) to join their Electronic Products team in California. The role involves designing and implementing verification environments using UVM & System Verilog, developing self-checking test benches, creating functional coverage models, conducting code coverage analysis, and setting up regression tests. The engineers will collaborate with cross-functional teams and may assist in FPGA-based prototyping and validation. The position requires a Bachelor's degree in a relevant engineering or science field and proven experience in ASIC/FPGA verification processes, SystemVerilog/UVM, and Object-Oriented Programming principles.

What you'd actually do

  1. Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
  2. Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards.
  3. Create Functional Coverage Models and conduct Code Coverage analysis to ensure thorough verification of designs during simulation.
  4. Set up regression tests and collect coverage metrics to ensure comprehensive verification and track progress over time.
  5. Assist in FPGA-based prototyping and validation based on program and system requirements and complexity.

Skills

Required

  • Bachelor of Science degree in Engineering (specializing in Electrical, Mechanical, or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry, or equivalent non-US qualifications
  • Proven experience in ASIC/FPGA verification processes
  • Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog/UVM
  • Proficiency in hardware verification languages, particularly SystemVerilog and SystemVerilog Assertions
  • Demonstrated experience in implementing test plans effectively
  • Solid understanding of Object-Oriented Programming principles, such as Inheritance and Polymorphism
  • Capability to design self-checking and reusable testbenches from the ground up
  • Experience in developing Functional Coverage Models and achieving Code Coverage closure
  • Capable of collaborating with design and system engineering to establish accurate and verifiable ASIC/FPGA level specifications
  • Familiarity with waveform debug tools
  • Revision Control Systems: svn, cvs, git
  • Proficient in Linux Environments

Nice to have

  • 5+ years of related work experience (Experienced, Level 3)
  • 10+ years of related work experience (Lead, Level 4)
  • Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience
  • Experience with hardware-based integration and test of ASIC/FPGA designs
  • Experience with hardware emulators, especially Palladium
  • Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
  • Proficient in scripting languages: Make, Perl, Python, etc.
  • Familiarity with space-based design techniques and radiation mitigation
  • Demonstrated history of 1st pass success with ASIC designs