Asic Physical Design and Timing Engineer - New College Grad 2026

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

This role is for an ASIC Physical Design and Timing Engineer focused on NVIDIA's GPUs, CPUs, DPUs, and SoCs. The engineer will be responsible for driving physical design and timing analysis and closure, including synthesis, equivalence checking, floor-planning, timing constraints, and ECO implementation. While the company heavily utilizes AI, this specific role is in hardware engineering and does not directly involve building or shipping AI models.

What you'd actually do

  1. Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.
  2. Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
  3. Play a pivotal role in the success of our innovative projects and advancement of our technology. Work in a cross-functional environment interacting with multiple teams.

Skills

Required

  • Master's degree or higher in Electrical or Computer Engineering (or equivalent experience)
  • Proficiency in Timing and Static Timing Analysis (STA)
  • Hands-on experience in full-chip/sub-chip STA and timing convergence, timing constraints generation and management
  • Expertise with industry standard EDA and timing convergence tools

Nice to have

  • Proven experience in timing convergence for ASICs, CPUs, GPUs or Network processors
  • Knowledge of deep sub-micron process nodes
  • Proficiency in AI/LLM and programming languages
  • Experience in physical design and optimization e.g., synthesis, floorplanning, placement, CTS, routing, power, etc. is a plus