Asic Physical Design Engineer

Jane Street Jane Street · Quant · New York, NY · Software Engineering

Jane Street is seeking an ASIC Physical Design Engineer for their Ultra Low Latency team. This role involves designing, testing, and deploying advanced hardware, with a focus on owning the physical design flow end-to-end while also having the ability to read/write RTL and understand front-end/back-end design interactions. The ideal candidate has 8+ years of experience in modern physical design flows and is interested in leveraging software engineering techniques and better tools to improve the hardware design process.

What you'd actually do

  1. design, test, and deploy advanced hardware
  2. collaborate with people in areas across the firm, including trading, networking, and research infrastructure
  3. lead with physical design expertise but think like chip designers
  4. comfortable owning a PD flow end-to-end
  5. able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary

Skills

Required

  • 8+ years hands-on experience building and running modern physical design flows (e.g., floor planning, place and route, timing closure, physical verification, power analysis)
  • broad experience across PD to own a flow end-to-end and identify risks
  • ability to read and write RTL
  • understanding of how front-end design decisions affect physical implementation and vice versa
  • experience programming in a high-level language (Python, C++, Haskell, etc.)

Nice to have

  • experience exclusively in PD (less preferred)
  • experience on smaller teams where multiple hats were worn
  • familiarity with OCaml (will be taught)

What the JD emphasized

  • advanced hardware
  • Ultra Low Latency team
  • own a PD flow end-to-end
  • read and write RTL
  • reason about design decisions that cross the front-end/back-end boundary
  • worked across the stack
  • wear multiple hats
  • hardware development toolchain embedded in OCaml
  • 8+ years hands-on experience building and running modern physical design flows
  • broad enough experience across PD that you can own a flow end-to-end and know where the risks are
  • think about physical design in the context of the overall chip
  • using software engineering techniques to improve the hardware design process