Asic Physical Design Engineer

Jane Street Jane Street · Quant · London, United Kingdom · Software Engineering

Jane Street is hiring an ASIC Physical Design Engineer to join their Ultra Low Latency team. This role involves designing, testing, and deploying advanced hardware, with an emphasis on owning the physical design flow end-to-end while also having the ability to read/write RTL and understand cross-functional design decisions. The team utilizes Hardcaml, a hardware development toolchain embedded in OCaml, and seeks engineers interested in improving hardware design processes with software engineering techniques.

What you'd actually do

  1. design, test and deploy advanced hardware
  2. collaborate with people in areas across the firm, including trading, networking and research infrastructure
  3. lead with physical design expertise but think like chip designers
  4. owning a PD flow end-to-end
  5. read and write RTL and reason about design decisions that cross the front-end/back-end boundary

Skills

Required

  • 8+ years hands-on experience building and running modern physical design flows (e.g., floorplanning, place and route, timing closure, physical verification, power analysis)
  • read and write RTL
  • understand how front-end design decisions affect physical implementation
  • experience programming in a high-level language (Python, C++, Haskell, etc.)
  • Fluent in English

Nice to have

  • OCaml

What the JD emphasized

  • advanced hardware
  • Ultra Low Latency team
  • lead with physical design expertise but think like chip designers
  • owning a PD flow end-to-end
  • read and write RTL and reason about design decisions that cross the front-end/back-end boundary
  • worked across the stack
  • wear multiple hats
  • hardware engineers who are excited about the advantages that better tools can bring
  • willing to try new things as a result
  • 8+ years hands-on experience building and running modern physical design flows
  • broad enough experience across PD that you can own a flow end-to-end and know where the risks are
  • read and write RTL and understand how front-end design decisions affect physical implementation—and vice versa
  • think about physical design in the context of the overall chip, not just as a downstream consumer of a netlist
  • using software engineering techniques to improve the hardware design process