Asic Physical Design Methodology Engineer

NVIDIA NVIDIA · Semiconductors · Shanghai, China

NVIDIA is hiring ASIC Physical Design Methodology Engineers in Shanghai, China. The role involves physical design from RTL to GSDII, including design quality check, synthesis, formal check, partitioning, constraint management, async check, timing analysis/fixing/signoff, and related flows. Responsibilities include developing timing analysis and closure methodologies, implementing flow automation, establishing methodologies for timing constraints, evaluating EDA tools, developing flows for PT-spice regression and silicon correlation, and developing flows/recommendations for STA and PNR in deep submicron physical effects. The role requires a Master's or PhD in Electrical Engineering or Computer Engineering with 2+ years of experience in physical design implementation, proven experience in synthesis, timing constraints, analysis, and closure, advanced proficiency in commercial STA tools, solid expertise in STA principles and signoff processes, hands-on experience in advanced CMOS technologies, and proficiency in at least one programming/scripting language.

What you'd actually do

  1. Develop timing analysis and timing closure methodologies, and implement flow automation for large-scale, high-speed semicustom chips based on deep submicron processes.
  2. Establish methodologies for timing constraints and SDC (release, including automatic constraint generation, constraint linting, and validation of timing exceptions.
  3. Take responsibility for EDA tool evaluation and collaborate with EDA vendors to enhance commercial timing signoff tools, constraint lint tools and spice simulation tools.
  4. Develop and validate flows for PT-spice regression, silicon correlation for high-speed designs.
  5. Develop flows/recommendations on STA and PNR in deep submicron physical effects aging, IR drop, crosstalk, noise and etc.

Skills

Required

  • Master's or PhD degree in Electrical Engineering or Computer Engineering
  • 2+ years of hands-on experience in physical design implementation
  • Proven experience in synthesis, timing constraints definition, timing analysis, and timing closure
  • Advanced proficiency in commercial STA tools, such as Synopsys PrimeTime, Spice, Redhawk, Cadence Tempus, Synopsys TCM, or Ausdia TimeVision
  • Solid expertise in STA principles and timing signoff processes including good knowledge of crosstalk analysis, IR-drop, electro-migration, noise, OCV, timing margins
  • Hands-on experience in advanced CMOS technologies, design with FinFET technology 7nm/5nm/3nm and beyond
  • Proficiency in at least one programming/scripting language, including Perl, TCL, Python, or C++
  • Strong verbal and written communication skills

Nice to have

  • Experience in flow development or automation for ASIC backend design

What the JD emphasized

  • deep submicron processes
  • timing constraints
  • timing signoff
  • advanced CMOS technologies
  • 7nm/5nm/3nm