In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will manage and lead a team of TFM engineers responsible for the physical design flows that power our Tensor Processing Unit (TPU) products. You will guide your team in developing, deploying, and supporting a register-transfer level (RTL)-to-GDS infrastructure. You will bridge design engineering and electronic design automation (EDA) capabilities, balancing resources and managing priorities across projects, feature requests, and bug resolutions to ensure silicon delivery.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Manage, mentor, and grow a team of tools, flows, and methodologies (TFM) engineers supporting custom silicon development for Tensor Processing Unit (TPU) products.
- Oversee the physical design methodology, driving the development and optimization of flows including place and route (P&R), RC extraction, logic equivalency checking (LEC), static timing analysis (STA), EMIR, and physical verification.
- Triage and manage team priorities across tapeouts, balancing flow bugs, feature developments, and methodology improvements.
- Collaborate with internal physical design (PD) execution teams, register-transfer level (RTL) designers, and external electronic design automation (EDA) vendors to troubleshoot flow issues, improve tool quality of results (QoR), and drive vendor enhancements.
- Define and execute the roadmap for flow automation, runtime efficiency, and scalability across process nodes.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with the register-transfer level (RTL)-to-GDS process and industry-standard electronic design automation (EDA) tools, including Synopsys, Cadence, and Siemens suites.
- 6 years of experience in a people management role, managing a team of engineers within an application-specific integrated circuit (ASIC) design, semiconductor, or EDA environment.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience supporting tools, flows, and methodologies (TFM) for ASICs (e.g., artificial intelligence (AI) or machine learning (ML) accelerators) on process nodes.
- Proficiency with scripting and automation languages commonly used in EDA workflows, such as Python, Tcl, Perl, and Make.