Asic Rtl Integration and Netlisting Engineer - New College Grad 2026

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a New College Grad ASIC RTL Integration and Netlisting Engineer to drive physical design integration and implementation of CPUs, GPUs, and SoCs. Responsibilities include RTL integration, synthesis, physical netlist deliverables, and formal equivalence checking.

What you'd actually do

  1. You will drive physical design integration and implementation of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level.
  2. Drive RTL integration, synthesis, along with all physical netlist deliverables across various milestones.
  3. Drive formal equivalence checking, netlist quality checks, asynchronous checking including clock domain crossing checks and MTBF analysis, etc.

Skills

Required

  • Bachelor's degree or Master's in Electrical or Computer Engineering (or equivalent experience).
  • Strong understanding of RTL and RTL hierarchy and associated infrastructures.
  • Strong understanding of VLSI design.
  • Solid understanding of logic synthesis and associated verification such as equivalence checking.
  • Knowledge of gate level netlist verification and completeness with respect to power, testability, etc.
  • Hands-on experience and solid understanding of industry standard EDA tools.

Nice to have

  • Understanding in clock-domains, async interfaces and MTBF analysis.
  • Understanding of Physical Design flows, design constraints, timing and power convergence.
  • Proficiency in programming/scripting languages (Python, TCL etc) and/or AI tools (Cursor, Copilot, etc).