Asic/soc Design Engineer

AMD AMD · Semiconductors · San Jose, CA · Engineering

This role is for an ASIC/SoC Design Engineer at AMD, focusing on the microarchitectural design and RTL implementation of Adaptive SoC and FPGA configuration systems. The responsibilities include authoring specifications, RTL coding, collaborating with hardware/firmware/software teams, driving design through all phases of silicon development, and optimizing for performance, power, and area. While the company mentions AI and data centers as areas of focus, this specific role is in core hardware design and implementation, not directly building AI models or systems.

What you'd actually do

  1. Author detailed micro-architecture specification and own RTL implementation of next-gen FPGA Configuration controller.
  2. Collaborate with hardware, firmware, and software teams to ensure a robust and cohesive configuration solution.
  3. Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
  4. Integrate complex configuration blocks into full-chip environment, ensuring proper connectivity, clock domain crossings, power domain crossing
  5. Partner with verification teams to ensure comprehensive functional coverage.

Skills

Required

  • ASIC design
  • Verilog
  • System Verilog
  • SystemVerilog Assertions (SVA)
  • SDC timing constraints
  • scripting languages (Perl, Python, Makefile)

Nice to have

  • industry-standard on-chip interconnect protocols (AMBA AXI/AXI-S/APB)
  • industry-standard ASIC CAD tools
  • designs with multiple power domains and UPF
  • System level knowledge