Chip Lead, Silicon Co-design Group

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Chip Lead for their Silicon Co-Design Group. This role serves as the technical lead for silicon programs, focusing on end-to-end technical integrity, feature integration, bug resolution, and shaping the technical narrative. The position requires deep understanding of SoC and ASIC architecture, with expertise in subsystems like HBM, SerDes, power/thermal, or packaging. The role involves guiding technical decisions across functional boundaries without direct authority and translating complex issues for executive leadership. Experience with post-silicon bring-up, validation, or system integration leadership is essential, along with a track record of shipped silicon products.

What you'd actually do

  1. Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs.
  2. Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution.
  3. Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging.
  4. Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs.
  5. Shape the program’s technical narrative by surfacing key risks, trade-offs, and mitigations as decision-ready options for executive leadership.

Skills

Required

  • BS or MS (or equivalent experience) in Electrical or Computer Engineering
  • 12+ years of experience
  • End-to-end understanding of SoC and ASIC architecture
  • Expertise in at least one subsystem (HBM, SerDes, power and thermal, or packaging)
  • Experience in post-silicon bring-up, validation, or system integration leadership
  • Experience with multiple shipped silicon products
  • Ability to guide technical decisions across functional boundaries without direct reporting authority
  • Ability to translate sophisticated silicon issues into clear options for executive audiences

Nice to have

  • Prior experience as a Chip Lead, Project Tech Lead, or Principal or Distinguished Engineer on a flagship GPU, AI accelerator, CPU, networking ASIC, or other large SoC
  • Patents, conference papers, invited talks, or recognized contributions to silicon validation, post-silicon debug, or co-design integration
  • History of building and sharing technical methodology beyond a single program
  • Hands-on debug experience with HBM, high-speed I/O, power and thermal, or packaging
  • Comfort working through ambiguity with globally distributed teams
  • Habit of surfacing the right risks and recommendations to leadership without being asked
  • Using AI tools to lift team velocity

What the JD emphasized

  • over a decade of proven track record in post-silicon bring-up, validation, or system integration leadership
  • multiple shipped silicon products
  • recognized expertise in at least one subsystem
  • Specific examples of silicon-level impact
  • track record of guiding technical decisions across functional boundaries without direct reporting authority